Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses

• US 5,644,496 A
• Filed: 06/18/1993
• Issued: 07/01/1997
• Est. Priority Date: 08/15/1989
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wright, Michael J., Agrawal, Om P.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/080,658
• Time in Patent Office: 1,474 Days
• Field of Search: 364/488, 364/489, 364/490, 364/716, 364/578, 395/500, 326/39, 326/41, 340/825.83
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP'"'"'s) are distributed symmetrically among the N·M crosspoints such that a same first number of interconnect switches (PIP'"'"'s) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP'"'"'s) are further distributed among the N·M crosspoints such that a same second number of interconnect switches (PIP'"'"'s) are found along each of the M output lines thereby providing equal loading on each output line.

Claims

1. A user-programmable device comprising:

(a) a monolithic substrate having logic and interconnect circuitry provided thereon;

(b) a first plurality of first through Nth Input/Output Blocks (IOB'"'"'s) provided on the substrate for receiving output signals of the substrate interconnect circuitry and coupling the output signals to points outside the substrate, and for receiving input signals from points outside the substrate and supplying the received input signals to the substrate interconnect circuitry;

(c) where the substrate interconnect circuitry includes at least one longline bus extending over or next to the first plurality of IOB'"'"'s, the at least one longline bus having first through Mth longlines, each extending over or next to the first plurality of IOB'"'"'s;

(d) where the Substrate interconnect circuitry further includes bus multiplexing means for selectively coupling respective ones of the first plurality of N IOB'"'"'s bidirectionally to preselected ones of the first through Mth longlines of the at least one longline bus, the bus multiplexing means providing selective bidirectional coupling between at least one of the longlines in the at least one longline bus and a programmably selected one or the other of two IOB'"'"'s among said first plurality of IOB'"'"'s such that signal propagation delay between the at least one longline and the programmably selected one or another of said two IOB'"'"'s is substantially the same irrespective of which of the two IOB'"'"'s is selected; and

(e) where said logic includes a first plurality of first through Kth logic blocks (CLB'"'"'s) operatively coupled to respective ones of the first through Mth longlines of the at least one longline bus.

2. The user-programmable device of claim 1 wherein

(d.1) the bus multiplexing means has a limited connectivity function such that, with respect to programmably-routable connections between CLB'"'"'s and IOB'"'"'s and for i equal to 0 through k, each CLB-i of the first through kth logic blocks (CLB'"'"'s) is programmably connectable to only a cluster of IOB'"'"'s, the cluster consisting of two or more but less than all of said first plurality of N IOB'"'"'s.

3. The user-programmable device of claim 2 wherein the number of IOB'"'"'s in a cluster is equal to or less than N/2.

4. The user-programmable device of claim 1 wherein the number of longlines, M is at least four.

5. The user-programmable device of claim 4 wherein M is at least eight.

6. The user-programmable device of claim 4 wherein the number of CLB'"'"'s, K is at least four.

7. The user-programmable device of claim 1 wherein the number of IOB'"'"'s, N is at least four.

8. The user-programmable device of claim 7 wherein N is at least eight.

9. A user-programmable device according to claim 1 wherein:

(c.1) the substrate interconnect circuitry further includes a second longline bus extending by the first plurality of IOB'"'"'s, the second longline bus having respective first through Mth longlines, each extending by the first plurality of IOB'"'"'s;

(d.1) said bus multiplexing means is further for selectively coupling respective ones of the first plurality of N IOB'"'"'s to preselected ones of the respective first through Mth longlines of the second longline bus,

the bus multiplexing means providing selective coupling between at least one of the respective longlines in the second longline bus and a programmably selected one or the other of said two IOB'"'"'s among said first plurality of IOB'"'"'s such that signal propagation delay between the respective at least one longline of the second longline bus and the programmably selected one or the other of the two IOB'"'"'s is substantially the same irrespective of which of the two IOB'"'"'s is selected,

and further such that signal propagation delay is substantially the same between the selected one of the two IOB'"'"'s and either of the selectively coupled longlines in the respective one and second longline buses irrespective of whether such selective coupling is established between the selected IOB and one or the other or both of the two longline buses.

10. A user-programmable device according to claim 9 wherein:

(e.1) said first plurality of first through Kth logic blocks (CLB'"'"'s) is further operatively coupled to respective ones of the first through Mth longlines of the second longline bus in a manner similar to the coupling of the first plurality of logic blocks to corresponding ones of the first through Mth longlines of the one longline bus such that a plurality of K or fewer signals may be transferred with a substantially same time delay between a corresponding K or fewer of the first plurality of logic blocks and either of the one and second longline buses.

11. The user-programmable device of claim 10 wherein the number of longlines, M in each of the one and second longline buses is equal to at least four.

12. The user-programmable device of claim 11 wherein the number N, of IOB'"'"'s in said first plurality of IOB'"'"'s is at least eight.

13. The user-programmable device of claim 10 wherein the first plurality of N IOB'"'"'s and the first plurality of K logic blocks are symmetrically couplable to the one and second longline buses such that said plurality of K or fewer signals may be transferred with a substantially same time delay between the corresponding K or fewer of the first plurality of logic blocks and a subset of K or fewer of the first plurality of N IOB'"'"'s over a corresponding one or the other of the one and second longline buses.

14. The user-programmable device of claim 13 wherein the first plurality of N IOB'"'"'s and the first plurality of K logic blocks are symmetrically couplable to the one and second longline buses such that said plurality of K or fewer signals may be transferred with said substantially same time delay between the corresponding K or fewer of the first plurality of logic blocks and the subset of K or fewer of the first plurality of N IOB'"'"'s over either of the one and second longline buses.

15. A user-programmable device according to claim 1 wherein:

(d.1) said bus multiplexing means provides evenly-distributed but partially-populated, selective cross-bar coupling between said first plurality of N IOB'"'"'s and said first plurality of M longlines.

16. A user-programmable device according to claim 15 wherein:

(d.2) said bus multiplexing means further provides evenly-distributed but partially-populated cross-bar coupling between said first plurality of K CLB'"'"'s and said first plurality of M longlines.

17. A user-programmable device according to claim 1 wherein:

(c.1) capacitive loading on each of said first through Mth longlines is essentially the same.

18. A user-programmable device according to claim 1 further comprising:

(f) a second plurality of first through Nth Input/Output Blocks (IOB'"'"'s) provided on the substrate for receiving further output signals of the substrate interconnect circuitry and coupling the further output signals to points outside the substrate, or for receiving further input signals from points outside the substrate and supplying the received further input signals to the substrate interconnect circuitry;

(g) where the substrate interconnect circuitry includes a second longline bus extending by the second plurality of IOB'"'"'s, the second longline bus having first through Mth further longlines, each extending by the second plurality of IOB'"'"'s;

(h) where the substrate interconnect circuitry additionally includes second bus multiplexing means for selectively coupling respective ones of the second plurality of N IOB'"'"'s to preselected ones of the first through Mth further longlines of the second longline bus, the second bus multiplexing means providing selective coupling between at least one of the longlines in the second longline bus and a programmably selected one or another of two further IOB'"'"'s among said second plurality of IOB'"'"'s such that signal propagation delay between the at least one further longline and the programmably selected one or the other of said two further IOB'"'"'s is substantially the same irrespective of which of the two further IOB'"'"'s is selected.

19. A user-programmable device according to claim 18 wherein said logic further includes:

(i) a second plurality of first through Kth logic blocks (CLB'"'"'s) operatively coupled to respective ones of the first through Mth longlines of the second longline bus.

20. A user-programmable device according to claim 1 wherein each of said K logic blocs is a programmably-configurable logic block.

21. A user-configurable switch matrix for use in a user-configurable logic device;

said switch matrix comprising;

a first plurality of N substantially parallel, first lines, where N is a number equal to or greater than four;

a second plurality of M substantially parallel, second lines intersecting with the plurality of N first lines to form N·

M intersection points, where M is a number equal to or greater than four; and

a third plurality of J, user-programmable interconnect means dispersed among the N·

M intersection points, where J is a number equal to or greater than eight but less than N·

M;

wherein each user-programmable interconnect means is programmable for either creating a connection between the intersecting lines of its intersection point or leaving an open circuit between the intersecting lines at its intersection point; and

wherein the J user-programmable interconnect means are dispersed among the N·

M intersection points such that each first line of the first plurality of N lines has a substantially same number of user-programmable interconnect means dispersed along the length of that first line so that each of the N first lines has a substantially same signal propagation delay.

22. A user-configurable switch matrix according to claim 21

wherein the J user-programmable interconnect means are dispersed among the N·

M intersection points such that each second line of the second plurality of M lines has a substantially same number of user-programmable interconnect means dispersed along the length of that second line so that each of the M second lines has a substantially same signal propagation delay.

23. A user-configurable switch matrix according to claim 22

wherein the user-configurable logic device has a plurality of N input/output pins respectively and operatively coupled to the N first lines such that an externally-sourced signal applied to a given one of said input/output pins can be routed from the given pin through the corresponding first line and through one or more of the user-programmable interconnect means to a respective one or more of the second lines with a substantially same signal propagation delay time irrespective of which one or more of the second lines is chosen as a destination for the routed signal.

24. A user-configurable switch matrix according to claim 22 wherein the user-configurable logic device includes:

a plurality of N/2 input/output blocks each having a bidirectional I/O terminal, a signal outputting terminal and two signal inputting terminals, the two signal inputting terminals of the N/2 input/output blocks being respectively coupled to the N first lines;

a plurality of N/2 input/output pins respectively and operatively coupled to the bidirectional I/O terminals of the N/2 input/output blocks such that an externally-sourced signal applied to a given one of said input/output pins can be routed from the given pin through the corresponding input/output block, through the corresponding first line and through one or more of the user-programmable interconnect means to a respective one or more of the second lines with a substantially same signal propagation delay time irrespective of which one or more of the second lines is chosen as a destination for the routed signal.

25. A user-configurable switch matrix according to claim 22

wherein the user-configurable logic device includes a user-programmable logic block operatively coupled to receive input signals from two or more of the second lines.

26. A user-configurable logic device comprising:

an input switch matrix;

a user-programmable logic block operatively coupled to receive input signals from the input switch matrix, the user-programmable logic block having a plurality of M'"'"' result output lines for outputting result signals formed by logic operations performed on the input signals received from the input switch matrix, where M'"'"' is a number equal to or greater than four;

an output switch matrix formed by a plurality of N'"'"' substantially parallel, output buses intersecting with the M'"'"' result output lines, where N'"'"' is a number equal to or greater than four, where each output bus has a plurality of N" substantially parallel output lines, where N" is a number equal to or greater than four, and where each output bus has associated therewith a bus access node to which a signal from a selected output line of the bus is to be supplied;

the output switch matrix further including a plurality of J'"'"', user-programmable interconnect means dispersed among N'"'"'·

M'"'"'·

N" intersection points formed by the intersections of the M'"'"' result output lines with the N'"'"'·

N" output lines of the output buses, where J'"'"' is a number equal to or greater than eight but less than N'"'"'·

M'"'"'·

N";

wherein each user-programmable interconnect means is programmable for either creating a connection between the intersecting result output line of its intersection point and the associated bus access node or leaving an open circuit between the intersecting result output line at its intersection point and the associated bus access node; and

wherein the J'"'"' user-programmable interconnect means are dispersed among the N'"'"'·

M'"'"'·

N" intersection points such that each result output line of the plurality of M'"'"' result output lines has a substantially same number of user-programmable interconnect means dispersed along the length of that result output line so that each of the M'"'"' result output lines has a substantially same signal propagation delay.

27. A user-configurable logic device according to claim 26

wherein the user-configurable logic device has a plurality of N'"'"' input/output pins respectively and operatively coupled to the N'"'"' bus access nodes of the output switch matrix such that an internally-sourced signal generated on a given one of M'"'"' result output lines can be routed to a desired one or more of the N'"'"' input/output pins through one or more of the user-programmable interconnect means and a respective one or more of the output lines of the N'"'"' output buses with a substantially same signal propagation delay time irrespective of which one or more of the N'"'"' input/output pins is chosen as a destination for the routed result signal.

28. A user-configurable logic device comprising:

a package;

a first number of I/O leads extending through the package for carrying signals between points inside and outside the package, said first number of I/O leads being partitionable at a given instant into a first subset of input leads and a second subset of output leads;

logic means within the package for executing pre-defined logic operations, the user-configurable logic means having a second number of logic input terminals for receiving logic input signals and a third number of logic output terminals for outputting logic output signals responsive to the logic input signals, said pre-defined logic operations defining a relation between the logic input and output signals, wherein the sum of the second and third numbers is greater than the first number; and

user-configurable signal routing means within the package for programmably routing signals between the I/O leads and user-defined, corresponding ones of the logic input terminals and the logic output terminals, and through such routing, programmably partitioning the first number of I/O leads into said first subset of input leads and said second subset of output leads;

wherein the user-configurable signal routing means includes consistent-routing delay means for maintaining substantially same signal propagation delays for all logic input signals as measured from the user-defined first subset of input leads to corresponding ones of the logic input terminals irrespective of the input signal routing configuration selected by the user, and for maintaining substantially same signal propagation delays for all logic output signals as measured between the user-defined second subset of output leads and corresponding ones of the logic output terminals irrespective of the output signal routing configuration selected by the user.

29. A user-configurable logic device according to claim 28

wherein the logic means includes consistent logic-delay means for maintaining substantially same signal propagation delays through the logic means for all logic input and output signals as measured from the logic input terminals to the logic output terminals, irrespective of the logic operations performed by the logic means.

30. A user-configurable logic device according to claim 29

wherein the logic means includes a plurality of user-configurable logic blocks each for executing user-defined logic operations.

31. A user-configurable logic device comprising:

a package;

a first number of I/O leads extending through the package for carrying signals between points inside and outside the package, said first number of I/O leads being partitionable at a given instant in time into a first subset of input leads and a second subset of output leads;

user-configurable logic means within the package for executing user-defined logic operations, the user-configurable logic means having a second number of logic input terminals for receiving logic input signals and a third number of logic output terminals for outputting logic output signals responsive to the logic input signals, said user-defined logic operations defining a relation between the logic input and output signals, wherein the sum of the second and third numbers is greater than the first number, and wherein the third number is greater than the maximum number of I/O leads that can serve at a given instant as said second subset of output leads; and

user-configurable output-signal routing means within the package for routing logic output signals from a user-defined subset of the logic output terminals to a corresponding, user-defined subset of the I/O leads, said user-defined subset of the I/O leads serving as the second subset of output leads;

wherein the user-configurable output-signal routing means includes consistent output-delay maintenance means for maintaining substantially same signal propagation delays for all logic output signals as measured between the user-defined second subset of output leads and corresponding ones of the logic output terminals irrespective of the output signal routing configuration selected by the user.

32. A user-configurable logic device according to claim 31

wherein the user-configurable output-signal routing means includes means for programmably routing the logic output signal of each logic output terminal to a programmably selectable one or more of a predefined cluster of the I/O leads, said predefined cluster of I/O leads defining an output cluster of I/O leads having a number of I/O leads that is smaller than the first number.

33. A user-configurable logic device according to claim 32

wherein the respective output clusters of logic output terminals distribute uniformly across substantially the full set of available I/O leads of said package.

34. A user-configurable logic device according to claim 33

wherein the number of I/O leads in each output cluster is less than or equal to one-half the first number.

35. A user-configurable logic device according to claim 32

wherein the number of I/O leads in each output cluster is less than or equal to one-half the first number.

36. A user-configurable logic device comprising:

a package;

a first number of I/O leads extending through the package for carrying signals between points inside and outside the package, said first number of I/O leads being partitionable at a given instant in time into a first subset of input leads and a second subset of output leads;

user-configurable logic means within the package for executing user-defined logic operations, the user-configurable logic means having a second number of logic input terminals for receiving logic input signals and a third number of logic output terminals for outputting logic output signals responsive to the logic input signals, said user-defined logic operations defining a relation between the logic input and output signals, wherein the sum of the second and third numbers is greater than the first number, and wherein the second number is greater than the maximum number of I/O leads that are available to serve at a given instant as said first subset of input leads; and

user-configurable input-signal routing means within the package for routing logic input signals from a user-defined subset of the I/O leads to a corresponding, user-defined subset of the logic input terminals, said user-defined subset of the I/O leads serving as the first subset of input leads;

wherein the user-configurable input-signal routing means includes consistent input-delay maintenance means for maintaining substantially same signal propagation delays for all logic input signals as measured between the user-defined first subset of input leads and corresponding ones of the logic input terminals irrespective of the input signal routing configuration selected by the user.

37. A user-configurable logic device according to claim 36

wherein the user-configurable input-signal routing means includes means for programmably routing the logic input signal of each I/O lead that serves as an input lead to a programmably selectable one or more of a predefined cluster of the logic input terminals, said predefined cluster of logic input terminals defining an input cluster of logic input terminals having a number of logic input terminals that is smaller than the first number.

38. A user-configurable logic device according to claim 37

wherein the respective input clusters of logic input terminals distribute uniformly across substantially the full set of available I/O leads of said package.

39. A user-configurable logic device according to claim 38

wherein the number of logic input terminals in each input cluster is less than or equal to one-half the second number.

40. A user-configurable logic device according to claim 37

wherein the number of logic input terminals in each input cluster is less than or equal to one-half the second number.

41. A user-configurable logic device according to claim 40

wherein the user-configurable logic means includes a plurality of substantially identical user-configurable logic blocks each for executing user-defined logic operations;

wherein said second number of logic input terminals are uniformly subdivided among the plurality of substantially identical user-configurable logic blocks; and

wherein the number of logic input terminals of each input cluster that connects to a given I/O lead constitute less than one-half the number of logic input terminals entering a corresponding logic block.

42. A user-configurable logic device according to claim 37

wherein the user-configurable logic means includes a plurality of substantially identical user-configurable logic blocks each for executing user-defined logic operations;

and

wherein said second number of logic input terminals are uniformly subdivided among the plurality of substantially identical user-configurable logic blocks.

43. A user-programmable device comprising a monolithic substrate having provided thereon:

(a) a plurality of first through Nth input/output means for receiving output signals to be output from the substrate and for coupling the output signals to points outside the substrate, or for receiving input signals from points outside the substrate;

(b) a plurality of first through Kth configurable logic means each for carrying out a programmably-redefinable logic function;

(c) an interconnect structure for providing interconnections between said plurality of configurable logic means and said plurality of input/output means, the interconnect structure including;

(c.1) partially-populated crossbar means for selectively providing programmably-redefinable and bidirectional couplings between subsets of the N input/output means and respective subsets of the K configurable logic means,

wherein each combination of a subset of input/output means and a respectively cross-couplable subset of configurable logic means contains at least two of said plurality of N input/output means or at least two of said plurality of K configurable logic means, and

wherein signal propagation delay between each input/output means and each respectively cross-couplable configurable logic means is substantially the same irrespective of which of the N input/output means is selectively coupled to which of the K configurable logic means.

44. A user-programmable device according to claim 43 wherein each said combination of a predefined subset of input/output means and a respectively cross-couplable subset of configurable logic means contains:

a same first number of input/output means, and

a same second number of configurable logic means.

45. A user-programmable device according to claim 44 wherein:

K is greater than 4; and

each said combination of a predefined subset of input/output means and a respectively cross-couplable subset of configurable logic means contains at least four of said plurality of K configurable logic means.

46. A user-programmable device according to claim 43 wherein:

N is at least 4;

K is at least 4; and

each said combination of a predefined subset of input/output means and a respectively cross-couplable subset of configurable logic means contains at least two of said plurality of N input/output means or at least two of said plurality of K configurable logic means.

47. A user-programmable device according to claim 43 wherein:

N is at least 8;

K is at least 8; and

each said combination of a predefined subset of input/output means and a respectively cross-couplable subset of configurable logic means contains at least four of said plurality of N input/output means or at least two of said plurality of K configurable logic means.

48. A user-programmable device according to claim 43 wherein said partially-populated crossbar means includes:

(c.1a) a first plurality of M lines crossing with a second plurality of N lines to thereby define a plurality of M·

N crossing points;

(c.1b) a plurality of less than M·

N programmable interconnect elements partially-populating said M·

N crossing points in symmetrical fashion, each programmable interconnect element providing a programmably-redefinable interconnection between the crossing lines of the respectively populated crossing point, said symmetrical partially-populating of the M·

N crossing points being such that each line among said first plurality of M lines has essentially a same first number of programmable interconnect elements coupled thereto and such that each line among said second plurality of N lines has essentially a same second number of programmable interconnect elements coupled thereto.

49. A user-programmable device according to claim 43 wherein said programmable interconnect elements include electrically erasable and reprogrammable nonvolatile memory devices.