Timing shell generation through netlist reduction

• US 5,644,498 A
• Filed: 01/25/1995
• Issued: 07/01/1997
• Est. Priority Date: 01/25/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Ducaroir, Francois, Wu, Allen, Joly, Christian, Sarkari, Zarir
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/377,844
• Time in Patent Office: 888 Days
• Field of Search: 364/489, 364/488, 364/490, 364/491, 364/578, 364/580, 395/500, 395/550, 395/160, 395/157, 395/600, 395/800, 395/700, 395/920, 371/22.2, 371/25.1, 371/22.3, 371/22.1, 257/206, 257/210, 257/909, 361/792, 361/803
• US Class Current: 716/103
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.

Claims

1. An apparatus for reducing a netlist which defines circuit paths and cells in a first circuit to provide a timing shell having the same timing constraints as said netlist, the timing shell netlist representing a second circuit, said apparatus comprising:

a memory for storing the netlist; and

a processor connected to the memory for executing a program, to reduce the netlist to the timing shell netlist by removing entries in the netlist that correspond to cells that are internal to the first circuit, the removed entries being chosen such that the second circuit has the same inputs and outputs as the first circuit and the same timing constraints with respect to signals entering and leaving the inputs and outputs, respectively, and the second circuit having a different circuit functionality than said first circuit.

2. The apparatus of claim 1, wherein the processor recursively examine cells in the netlist along circuit paths connected to nets at each input and output of the circuit.

3. The apparatus of claim 1, wherein for a particular circuit path connected to a net at an input of the circuit, the processor preserves netlist entries corresponding to combinatorial cells between the input and a first storage element on the particular circuit path.

4. The apparatus of claim 3, wherein the processor preserves netlist entries corresponding to combinatorial cells coupled to a combinatorial path between the particular circuit path and a circuit boundary without an intervening storage cell.

5. The apparatus of claim 1, wherein for a particular circuit path coupled to an input and an output of the circuit, the processor preserves netlist entries corresponding to combinatorial cells on the particular circuit path which establish a combinatorial path between the input and the output.

6. The apparatus of claim 1, wherein for a particular net coupled by a first combinatorial circuit path from an output of a first storage cell in the circuit to a circuit boundary, in which the first storage cell is also coupled by a second combinatorial circuit path to an input of a second storage cell in the circuit, the processor preserves netlist entries corresponding to combinatorial cells on the first combinatorial circuit path and removes netlist entries corresponding to combinatorial cells on the second combinatorial circuit path.

7. The apparatus of claim 1, wherein the processor preserves clock, set and reset circuit paths within the netlist.

8. The apparatus of claim 1, wherein the processor preserves loading information about removed cells coupled to nets between preserved cells.

9. The machine of claim 1, wherein

for a particular circuit path connected to a net at an input of the first circuit, the processor preserves netlist entries corresponding to combinatorial cells between the input and a first storage element on that particular circuit path and combinatorial cells coupled to a combinatorial path between that particular circuit path and a circuit boundary without an intervening storage cell;

for a particular circuit path coupled to an input and an output of the first circuit, the processor preserves netlist entries corresponding to combinatorial cells on that particular circuit path which establish a combinatorial path between the input and the output;

for a particular net coupled by a first combinatorial circuit path from an output of a first storage cell in the first circuit to a circuit boundary, in which the first storage cell is also coupled by a second combinatorial circuit path to an input of a second storage cell in the first circuit, the processor preserves netlist entries corresponding to combinatorial cells on the first combinatorial circuit path and remove combinatorial cells on the second combinatorial circuit path, and

wherein the processor also preserves clock, set and reset circuit paths, loading information about nets coupled to removed cells and netlist entries corresponding to cells that must be preserved as determined by other criteria.

10. A method for operating a computing system to generate a timing shell netlist for a first circuit from a netlist which defines circuit paths and cell in the circuit, said timing shell netlist representing a second circuit, the method comprising the steps of recursively examining cells connected to nets at inputs and outputs of the circuit and removing internal cells meeting a set of criteria while preserving in the timing shell netlist information for timing analysis of a system incorporating the circuit, the second circuit having a different circuit functionality than the first circuit.

11. The method of claim 10 wherein the set of criteria includes:

for a particular circuit path connected to a net at an input of the first circuit, preserve combinatorial cells between the input and a first storage element on the particular circuit path and preserve combinatorial cells coupled to a combinatorial path between the particular circuit path and a circuit boundary without an intervening storage cell;

for a particular circuit path coupled to an input and an output of the first circuit, preserve combinatorial cells on the particular circuit path which establish a combinatorial path between the input and the output;

for a particular net coupled by a first combinatorial circuit path from an output of a first storage cell in the first circuit to a circuit boundary, in which the first storage cell is also coupled by a second combinatorial circuit path to an input of a second storage cell in the first circuit, preserve combinatorial cells on the first combinatorial circuit path and remove combinatorial cells on the second combinatorial circuit path;

preserve clock, set and reset circuit paths of the first circuit; and

preserve loading information about nets coupled to removed cells and preserved cells of the first circuit.

12. The method of claim 10, wherein the step of examining includes:

for a particular net at an input of the first circuit, examining each cell connected to the particular net, and if the cell is a storage element, and the particular net carries a clock, set or reset signal, save a netname and loading information about the particular net, else preserve the cell and proceed with other cells connected to the particular net if any, then proceed with other inputs;

if the cell is not a storage element, preserve the cell and examine each cell on each net connected to an output of the preserved cell, then proceed with other cells connected to the particular net if any, then proceed with other inputs; and

for a particular net at an output of the first circuit, examine each cell connected to the particular net, and if the particular net is connected to an input of the cell, then preserve a netname and loading information about the particular net, then proceed with other cells connected to the particular net if any, then proceed with other outputs;

if the particular net is connected to an output of the cell and the cell is a storage element, then preserve the cell, else preserve the cell and examine each cell on each net connected to an input of the preserved cell, then proceed with other cells connected to the particular net if any, then proceed with other outputs.