Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation

• US 5,644,515 A
• Filed: 06/07/1995
• Issued: 07/01/1997
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Sample, Stephen P., D'Amour, Michael R., Payne, Thomas S.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/483,337
• Time in Patent Office: 755 Days
• Field of Search: 364/578, 364/580, 364/579, 340/825.22, 340/825.88, 340/825.89, 340/825.06, 340/825.83, 340/825.84, 365/201
• US Class Current: 703/23
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user'"'"'s circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Claims

1. A apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said apparatus comprising:

a plurality of fixed electrical conductors;

a plurality of reprogrammable logic chips, each of said plurality of reprogrammable logic chips comprising input/output terminals, at least some of said input/output terminals of said plurality of reprogrammable logic chips connected to said fixed electrical conductors, said plurality of reprogrammable logic chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals;

an input/output bus; and

a plurality of reconfigurable probe chips, each of said reconfigurable probe chips comprising input/output terminals, a first group of said input/output terminals of said plurality of reconfigurable probe chips connected to said input/output bus, a second group of said input/output terminals of said plurality of reconfigurable probe chips connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said plurality of reconfigurable probe chips in electrical communication with at least some of said input/output terminals of said plurality of reprogrammable logic chips, said reconfigurable probe chips transferring state information from a node within said reprogrammable functional logic elements onto said input/output bus.

2. The apparatus of claim 1 wherein said plurality of reprogrammable logic chips comprise field programmable gate arrays.

3. The apparatus of claim 1 wherein said plurality of reconfigurable probe chips comprise field programmable gate arrays.

4. The apparatus of claim 1 wherein said plurality of reprogrammable logic chips and said plurality of reconfigurable probe chips comprise field programmable gate arrays.

5. A hardware logic emulation apparatus comprising:

a plurality of fixed electrical conductors;

an array of reprogrammable chips comprising a first column of reprogrammable chips and a second column of reprogrammable chips, each of said reprogrammable chips comprising input/output terminals, at least some of said input/output terminals of said reprogrammable chips connected to said fixed electrical conductors, at least some of said reprogrammable chips further comprising reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals;

an input/output bus;

a first reconfigurable probe chip, said first reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said first reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said first reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said first reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said first column, said first reconfigurable probe chip transferring state information from a node of said reprogrammable functional logic elements in said reprogrammable chips in said first column onto said input/output bus

a second reconfigurable probe chip, said second reconfigurable probe chip comprising input/output terminals, a first group of said input/output terminals of said second reconfigurable probe chip connected to said input/output bus, a second group of said input/output terminals of said second reconfigurable probe chip connected to said fixed electrical conductors, said fixed electrical conductors placing said second group of said input/output terminals of said second reconfigurable probe chip in electrical communication with at least one of said input/output terminals of said reprogrammable chips in said second column; and

said reconfigurable probe chips transferring state information from a node of said reprogrammable functional logic elements onto said input/output bus.

6. An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising:

a plurality of fixed electrical conductors;

a plurality of first field programmable gate arrays, said first field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable functional logic elements capable of being connected to at least some of said input/output terminals;

a plurality of second field programmable gate arrays, said second field programmable gate arrays comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected functional logic elements in one of said first field programmable gate arrays to selected functional logic elements in another of said first field programmable gate arrays containing functional logic elements;

an input/output bus; and

a third field programmable gate array, said third field programmable gate array comprising input/output terminals connected to said fixed electrical conductors and reprogrammable electrical conductors connected to at least some of said input/output terminals for reconfigurably interconnecting selected nodes in one of said first field programmable gate arrays to said input/output bus.

7. An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted for use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising:

a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices having reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said electrically reconfigurable devices having reprogrammable functional logic elements further comprising nodes capable of being connected to a probe terminal;

at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected of said electrically reconfigurable devices having functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices having functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices having functional logic elements; and

a probe for muting signals from said probe terminal to a bus.

8. The apparatus of claim 7 wherein said probe comprises at least one probe electrically reconfigurable device, said probe electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect said nodes of selected of said electrically reconfigurable devices having functional logic elements such that selected nodes in one of said selected electrically reconfigurable devices having functional logic elements can be electrically coupled to said input/output bus.

9. The apparatus of claim 7 wherein said apparatus further comprises a plurality of fixed electrical conductors, at least one of said plurality of fixed electrical conductors in electrical communication with said probe terminal.

10. The apparatus of claim 9 wherein said probe comprises at least one probe electrically reconfigurable device, said probe electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect said fixed electrical conductors in electrical communication with said probe terminal of selected of said electrically reconfigurable devices having functional logic elements such that signals at said probe terminal can be electrically coupled to said input/output bus.

11. An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information and which transmits signal information between the configured circuit design and an external system adapted or use with a component incorporating the circuit design, said electrically reconfigurable hardware emulation apparatus comprising:

a plurality of fixed electrical conductors;

an input/output bus;

a plurality of field programmable gate arrays, at least some of said field programmable gate arrays having reprogrammable functional logic elements, said field programmable gate arrays having reprogrammable functional logic elements comprising nodes and a probe terminal connected to said fixed electrical conductors, said probe terminal capable of being connected to said nodes;

at least one other of said field programmable gate arrays containing reprogrammable electrical conductors connected to at least some of said fixed electrical conductors for reconfigurably interconnecting selected functional logic elements in one of said field programmable gate arrays having functional logic elements to selected functional logic elements in another of said field programmable gate arrays having functional logic elements; and

at least one other of said field programmable gate arrays containing reprogrammable electrical conductors which are used to reconfigurably interconnect said fixed electrical conductors in electrical communication with said probe terminal of said field programmable gate arrays having functional logic elements such that signals at said probe terminal can be electrically coupled to said input/output bus.