Program algorithm for low voltage single power supply flash memories

• US 5,644,531 A
• Filed: 11/01/1995
• Issued: 07/01/1997
• Est. Priority Date: 11/01/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kuo, Tiao Hua, Chang, Chung K., Chen, Johnny, Yu, James C. Y.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/551,705
• Time in Patent Office: 608 Days
• Field of Search: 365/185.11, 365/230.03, 365/185.33
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A programming algorithm for a flash memory wherein programming circuitry is subdivided into a set of separately controllable groups. The algorithm detects a number of logic zeros to be programmed into a flash cell array by each group and switches among the groups such that a number of simultaneously programmed cells in the flash cell array does not exceed a predetermined number and such that maximum available programming current is used to enhance programming speed.

Claims

1. A programming method for a memory, comprising the steps of:

subdividing programming circuitry in the memory into a set of groups;

detecting a number of logic zeros to be programmed into a cell array by each group;

switching among the groups such that a number of simultaneously programmed cells in the cell array does not exceed a predetermined number while using maximum available programming current provided by a low voltage, single power supply.

2. The programming method of claim 1, wherein the step of detecting a number of logic zeros comprises the step of detecting a number of logic zeros contained in a program byte targeted for the cell array.

3. The programming method of claim 2, wherein the program byte comprises a high byte of the cell array.

4. The programming method of claim 2, wherein the program byte comprises a low byte of the cell array.

5. The programming method of claim 1, wherein the step of detecting a number of logic zeros comprises the step of detecting a number of logic zeros contained in a program word targeted for the cell array.

6. The programming method of claim 1, wherein the memory is a low voltage single power supply flash memory.

7. A memory, comprising:

a single, low voltage power supply;

programming circuitry arranged into a set of separately controllable groups;

detection circuitry that detects a number of logic zeros to be programmed into a cell array by each group;

circuitry that switches among the groups such that a number of simultaneously programmed cells in the cell array does not exceed a predetermined number while using maximum available programming current generated by the low voltage power supply.

8. The memory of claim 7, wherein the circuitry that switches among the groups comprises a state machine.

9. The memory of claim 7, wherein the detection circuitry determines a number of logic zeros contained in a program byte targeted for the cell array.

10. The memory of claim 9, wherein the program byte comprises a high byte of the cell array.

11. The memory of claim 9, wherein the program byte comprises a low byte of the cell array.

12. The memory of claim 7, wherein the detection circuitry determines a number of logic zeros contained in a program word targeted for the cell array.

13. The memory of claim 7, wherein the cell array comprises a flash cell array for a low voltage single power supply flash memory.

14. The memory of claim 7, wherein the low voltage supply has a value in the range of 2.7 volts-3.0 volts.