Memory apparatus and data processor using the same

• US 5,644,699 A
• Filed: 03/13/1995
• Issued: 07/01/1997
• Est. Priority Date: 08/07/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Toyohiko
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US08/403,558
• Time in Patent Office: 841 Days
• Field of Search: 395/575, 395/182.05, 395/182.04, 395/182.03, 395/185.07, 364/243.6, 364/245.3, 364/268.3, 364/268.5, 364/943.91, 364/944.2, 364/970.1, 364/246.3, 371/8.1, 371/9.1, 371/10.1, 371/10.2, 371/10.3, 371/21.1, 371/21.2, 371/21.6
• US Class Current: 714/6.32
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input, terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory. Since the failure in the memory array unit can be relieved, manufacturing yields of the memory apparatus and the data processor including the same are improved.

Claims

1. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon start-up, said data processor having a data bus and an address bus and comprising:

(a) a reset signal input terminal into which a reset signal is input;

(b) a memory unit, coupled to said data bus, including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, said memory unit including a spare column of memory cells;

(c) a memory failure diagnosis circuit, coupled to said reset input terminal, to said memory unit, and to said data and address buses, for testing said memory unit for defective memory cells and replacing said defective memory cells in response to said reset signal, said memory failure diagnosis circuit including;

(1) a control program memory for storing a microprogram that controls operation of said memory failure diagnosis circuit, said microprogram beginning execution in response to said reset signal;

(2) a memory failure diagnosis sub-processor, coupled to said control program memory and to said data and address buses, for executing a plurality of operations to detect and replace defective memory cells according to said microprogram, and for ensuring that said plurality of operations are always executed in a predetermined number of cycles of said clock signal regardless of whether a defective memory cell is detected and replaced, said failure diagnosis subprocessor including;

a. a counter for counting said predetermined number of cycles of said clock signal and for generating a count termination signal when a last one of said predetermined number of cycles of said clock signal is counted;

b. a first register for storing a column address of said defective memory cells in said memory unit; and

c. an execution unit, coupled to said counter, for executing each of said plurality of operations until said count termination signal is received from said counter;

(3) a column replacing circuit, coupled to said memory failure diagnosis sub-processor, for replacing a defective column of said memory unit, as identified by said column address stored in said first register, with said spare column of memory cells.

2. The data processor set forth in claim 1 wherein said column replacing circuit comprises:

(a) a column register for storing a defective column address of said defective column as determined from said first register;

(b) a defective column decoder, coupled to said column register, for decoding said defective column address, and for generating a multiplexer control signal corresponding to said defective column address; and

(c) a bit-line multiplexer, having a control input coupled to said defective column decoder, a plurality of data terminals coupled to said data bus, and a plurality of memory terminals coupled to said plurality of columns of said memory unit, said plurality of memory terminals including a spare column terminal coupled to said spare column, said bit-line multiplexer selectively coupling one of said plurality of data terminals identified by said multiplexer control signal to said spare column terminal.

3. The data processor set forth in claim 1 wherein said plurality of memory columns includes a first memory column and a second memory column, and wherein:

when said memory failure diagnosis circuit finds a memory defect in said first column, a first value is written into said first register at an end of a predetermined time period;

when said memory failure diagnosis circuit finds a memory defect in said second column, a second value, different than said first value, is written into said first register at said end of said predetermined time period; and

when said memory failure diagnosis circuit finds no memory failures, a third value, different than said first and second values, is written into said first register at said end of said predetermined time period.

4. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon start-up, said data processor having a data bus and an address bus and comprising:

(a) a reset signal input terminal into which a reset signal is input;

(b) a memory unit, coupled to said data bus, including a plurality of memory cells arranged in a plurality rows and a plurality of columns, said memory unit including a spare row of memory cells;

(c) a memory failure diagnosis circuit, coupled to said reset input terminal, to said memory unit, and to said data and address buses, for testing said memory unit for defective memory cells and replacing said defective memory cells in response to said reset signal, said memory failure diagnosis circuit including;

(1) a control program memory for storing a microprogram that controls operation of said memory failure diagnosis circuit, said microprogram beginning execution in response to said reset signal;

(2) a memory failure diagnosis sub-processor, coupled to said control program memory and to said data and address buses, for executing a plurality of operations to detect and replace defective memory cells according to said microprogram and for ensuring that said plurality of operations are always executed in a fixed amount of time regardless of whether a defective memory cell is detected and replaced, said failure diagnosis sub-processor including;

a. a counter for counting a predetermined number of cycles of said clock signal, and for generating a count termination signal when a last one of said predetermined number of cycles of said clock signal is counted;

b. a first register for storing a row address of said defective memory cells in said memory unit; and

c. an execution unit, coupled to said counter, for executing each of said plurality of operations until said count termination signal is received from said counter;

(3) a row replacing circuit, coupled to said memory failure diagnosis sub-processor, for replacing a defective row of said memory unit, as identified by said row address in said first register, with said spare row of memory cells.

5. The data processor set forth in claim 4 wherein said plurality of memory column includes a first memory row and a second memory row, and wherein:

when said memory failure diagnosis circuit finds a memory defect in said first row, a first value is written into said first register at an end of a predetermined time period;

when said memory failure diagnosis circuit finds a memory defect in said second row, a second value, different than said first value, is written into said first register at said end of said predetermined time period; and

when said memory failure diagnosis circuit finds no memory failures, a third value, different than said first and second values, is written into said first register at said end of said predetermined time period.

6. The data processor set forth in claim 4 wherein said row replacing circuit comprises:

a) a row address decoder, coupled to said address bus, for decoding an input address on said data bus, and for generating one of a plurality of row activation signals, each of said plurality of row activation signals selecting one of said plurality of rows of said memory unit according to said input address;

b) an associative memory, coupled to said address bus, for storing a defective row address of said defective row as determined from said first register, and for generating a spare row activation signal to select said spare row when said input address matches said defective row address; and

c) a row access inhibiting unit, coupled to said row address decoder, to said associative memory, and to said memory unit, for selectively disabling any one of said plurality of row activation signals and said spare row activation signal.

7. The data processor set forth in claim 6 wherein when said spare row of memory cells is accessed, said row access inhibiting unit prevents said row activation signal from selecting said defective row of memory cells and allows said spare row activation signal to access said spare row.

8. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon start-up, said data processor having a data bus and an address bus and comprising:

(a) a reset signal input terminal into which a reset signal is input;

(b) a memory unit, coupled to said data bus, including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, said memory unit including a spare column of memory cells and a spare row of memory cells;

(c) a memory failure diagnosis circuit, coupled to said reset input terminal, to said memory unit, and to said data and address buses, for testing said memory unit for defective memory cells and replacing said defective memory cells in response to said reset signal, said memory failure diagnosis circuit including;

(1) a control program memory for storing a microprogram that controls operation of said memory failure diagnosis circuit, said microprogram beginning execution in response to said reset signal;

(2) a memory failure diagnosis sub-processor, coupled to said control program memory and to said data and address buses, for executing a plurality of operations to detect and replace defective memory cells according to said microprogram and for ensuring that said plurality of operations are always executed in a fixed amount of time regardless of whether a defective memory cell is detected and replaced, said failure diagnosis sub-processor including;

a. a counter for counting a predetermined number of cycles of said clock signal, and for generating a count termination signal when a last one of said predetermined number of cycles of said clock signal is counted;

b. a first register for storing a column address of said defective memory cells in said memory unit;

c. a second register for storing a row address of said memory cells in said memory unit; and

d. an execution unit, coupled to said counter, for executing each of said plurality of operations until said count termination signal is received from said counter;

(3) a column replacing circuit, coupled to said memory failure diagnosis subprocessor, for replacing a defective column of said memory unit, as identified by said column address stored in said first register, with said spare column of memory cells; and

(4) a row replacing circuit, coupled to said memory failure diagnosis subprocessor, for replacing a defective row of said memory unit, as identified by said row address stored in said second register, with said spare row of memory cells.

9. The data processing system set forth in claim 8 wherein:

said column replacing circuit comprises;

(a) a column register for storing a defective column address of said defective column as determined from said information stored in said first register;

(b) a defective column decoder, coupled to said column register, for decoding said defective column address, and for generating a multiplexer control signal corresponding to said defective column address; and

(c) a bit-line multiplexer, having a control input coupled to said defective column decoder, a plurality of data terminals coupled to said data bus, and a plurality of memory terminals coupled to said plurality of columns of said memory unit, said plurality of memory terminals including a spare column terminal coupled to said spare column, said bit-line multiplexer selectively coupling one of said plurality of data terminals identified by said multiplexer control signal to said spare column terminal; and

said row replacing circuit comprises;

(a) a row address decoder, coupled to said address bus, for decoding an input address on said address bus, and for generating one of a plurality of row activation signals, each of said plurality of row activation signals selecting one of said plurality of rows of said memory unit according to said input address;

(b) an associative memory, coupled to said address bus, for storing a defective row address of said defective row as determined from said information stored in said first register, and for generating a spare row activation signal to select said spare row when said input address matches said defective row address; and

(c) a row access inhibiting unit, coupled to said row address decoder, to said associative memory, and to said memory unit, for selectively disabling any one of said plurality of row activation signals and said spare row activation signal.

10. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon startup, said data processor having a data bus and an address bus and comprising:

a data buffer coupled to said data bus and said address bus, said data buffer including;

a memory unit, coupled to said data bus, including an array of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of columns including a spare column of memory cells and a plurality of main columns of memory cells;

a column replacing circuit, coupled to said address bus, said data bus, and said memory unit, for replacing one of said plurality of main columns determined to be a defective column with said spare column, said defective column containing at least one defective memory cell;

a reset signal input;

a non-volatile memory, coupled to said reset signal input, for storing a memory failure diagnosis microprogram and for generating a plurality of control signals according to said memory failure diagnosis microprogram when a reset signal is asserted at said reset signal input;

an operation unit, coupled to said non-volatile memory and to said address and data buses, for executing a plurality of operations to detect and replace defective memory cells in said memory unit, and for ensuring that said plurality of operations are always executed in fixed amount of time regardless of whether a defective memory cell is detected and replaced, said operation unit including;

a counter for counting a predetermined number of cycles of said clock signal;

an execution unit, coupled to said counter, for executing each of said plurality of operations responsive to said plurality of control signals and until said counter counts a last one of said predetermined number of cycles of said clock signal;

a first register for storing a defective column number identifying said defective column; and

a second register for storing data indicating the number of defective cells in said defective column.

11. The data processor of claim 10, wherein said column replacing circuit comprises:

a column register, coupled to said data bus, for storing said defective column number;

a defective column decoder, coupled to said column register, for decoding said defective column number and for generating one of a plurality of multiplexer control signals corresponding to said defective column number; and

a column multiplexer including;

a control input coupled to said defective column decoder;

a plurality of data terminals coupled to said data bus;

a plurality of memory terminals coupled to said plurality of columns of said memory unit, said plurality of memory terminals including a spare terminal coupled to said spare column; and

a switch circuit coupling said plurality of data terminals to said plurality of memory terminals, and selectively coupling one of said plurality of data terminals identified by said multiplexer control signal to said spare terminal.

12. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon startup, said data processor having a data bus and an address bus and comprising:

a data buffer coupled to said data bus and said address bus, said data buffer including;

a memory unit, coupled to said data bus, including an array of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of rows including a spare row of memory cells and a plurality of main rows of memory cells;

a row decoding unit, coupled to said address bus and to said memory unit, for accessing one of said plurality of main rows according to an input address on said address bus, and for accessing said spare row instead when said input address corresponds to a defective row address, said defective row address identifying one of said plurality of mains rows containing at least one defective memory cell;

a reset signal input;

a non-volatile memory, coupled to said reset signal input, for storing a memory failure diagnosis microprogram and for generating a plurality of control signals according to said memory failure diagnosis microprogram when a reset signal is asserted at said reset signal input;

an operation unit, coupled to said non-volatile memory and to said address and data buses, for executing a plurality of operations to detect and replace defective memory cells in said memory unit, and for ensuring that said plurality of operations are always executed in a fixed amount of time regardless of whether a defective memory cell is detected and replaced, said operation unit including;

a counter for counting a predetermined number of cycles of said clock signal;

an execution unit, coupled to said counter, for executing each of said plurality of operations responsive to said plurality of control signals and until said counter counts a last one of said predetermined number of cycles of said clock signal;

a first register for storing said defective row address; and

a second register for storing data indicating a total number of said plurality of rows having a defective memory cell detected therein.

13. The data processor of claim 12, wherein said row decoding unit comprises:

an associative memory, coupled to said address bus, for storing said defective row address, and for generating a spare row access signal when said input address on said address bus matches said defective row address;

a row address decoder, coupled to said address bus, for decoding said input address, and for generating one of a plurality of main row access signals according to said input address, each one of said plurality of main row access signals selecting one of said plurality of main rows of said memory unit; and

a row access enabling unit, coupled to said address decoder and said associative memory, for selectively disabling any one of said plurality of main row access signals and said spare row access signal.

14. A data processor regulated by a clock signal that automatically detects and replaces defective memory cells upon startup, said data processor having a data bus and an address bus and comprising:

a data buffer coupled to said data bus and said address bus, said data buffer including;

a memory unit, coupled to said data bus, including an array of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of rows including a spare row of memory cells and a plurality of main rows of memory cells, said plurality of columns including a spare column of memory cells and a plurality of main columns of memory cells;

a column replacing circuit, coupled to said address bus, said data bus, and said memory unit, for replacing one of said plurality of main columns determined to be a defective column with said spare column, said defective column containing at least one defective memory cell; and

a row decoding unit, coupled to said address bus and to said memory unit, for accessing one of said plurality of main rows according to an input address on said address bus, and for accessing said spare row instead when said input address corresponds to a defective row address, said defective row address identifying one of said plurality of mains rows containing at least one defective memory cell;

a reset signal input;

a non-volatile memory, coupled to said reset signal input, for storing a memory failure diagnosis microprogram and for generating a plurality of control signals according to said memory failure diagnosis microprogram when a reset signal is asserted at said reset signal input;

an operation unit, coupled to said non-volatile memory and to said address and data buses, for executing a plurality of operations to detect and replace defective memory cells in said memory unit, and for ensuring that said plurality of operations are always executed in a fixed amount of time regardless of whether a defective memory cell is detected and replaced, said operation unit including;

a counter for counting a predetermined number of cycles of said clock signal;

an execution unit, coupled to said counter, for executing each of said plurality of operations responsive to said plurality of control signals and until said counter counts a last one of said predetermined number of cycles of said clock signal;

a first register for storing a defective column number identifying said defective column; and

a second register for storing data indicating the number of defective cells in said defective column;

a third register for storing said defective row address; and

a fourth register for storing data indicating a total number of said plurality of rows having a defective memory cell detected therein.

15. The data processor of claim 14, wherein said column replacing circuit comprises:

a column register, coupled to said data bus, for storing said defective column number;

a defective column decoder, coupled to said column register, for decoding said defective column number and for generating one of a plurality of multiplexer control signals corresponding to said defective column number; and

a column multiplexer including;

a control input coupled to said defective column decoder;

a plurality of data terminals coupled to said data bus;

a plurality of memory terminals coupled to said plurality of columns of said memory unit, said plurality of memory terminals including a spare terminal coupled to said spare column; and

a switch circuit coupling said plurality of data terminals to said plurality of memory terminals, and selectively coupling one of said plurality of data terminals identified by said multiplexer control signal to said spare terminal; and

wherein said row decoder comprises;

an associative memory, coupled to said address bus, for storing said defective row address, and for generating a spare row access signal when said input address on said address bus matches said defective row address;

a row address decoder, coupled to said address bus, for decoding said input address, and for generating one of a plurality of main row access signals according to said input address, each one of said plurality of main row access signals selecting one of said plurality of main rows of said memory unit; and

a row access enabling unit, coupled to said address decoder and said associative memory, for selectively disabling any one of said plurality of main row access signals and said spare row access signal.

16. In a data processor having memory unit, a counter, and a register, said memory unit including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of rows including a spare row and said plurality of columns including a spare column, a method for automatically detecting and replacing defective memory cells in said memory unit upon startup comprising the steps of:

asserting a reset signal to indicate startup of said data processor;

executing a startup sequence in response to said reset signal, said startup sequence having a first part and a second part and including the steps of;

initializing said counter to count a predetermined number of cycles of a clock signal, wherein said predetermined number of cycles of said clock signal corresponds to said first part of said startup sequence;

generating a count termination signal when a last one of said predetermined number of cycles of said clock signal is counted;

detecting and replacing defective memory cells in said memory unit while said counter counts said predetermined number of cycles of said clock signal and until said count termination signal is generated, said step of detecting and replacing including;

setting each of said plurality of memory cells in said memory unit to a predetermined value;

reading out a stored value from each of said plurality of memory cells;

determining if said stored value and said predetermined value coincide for each of said plurality of memory cells;

storing data in said register to indicate a location of a particular one of said plurality of memory cells when said stored value and said predetermined value do not coincide for said particular one of said plurality of memory cells; and

replacing said location of said defective memory cell with one of said spare row and said spare column; and

executing said second part of said startup sequence only after said count termination signal has been generated regardless of whether a defective memory cell was identified in said detecting and replacing step.

17. In a data processor having memory unit, a counter, and a register, said memory unit including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of rows including a spare row and said plurality of columns including a spare column, and said plurality columns having column numbers associated therewith, a method for automatically detecting and replacing defective memory cells in said memory unit upon startup comprising the steps of:

asserting a reset signal to indicate startup of said data processor;

executing a startup sequence in response to said reset signal, said startup sequence having a first part and a second part and including the steps of;

initializing said counter to count a predetermined number of cycles of a clock signal, wherein said predetermined number of cycles of said clock signal corresponds to said first part of said startup sequence

generating a count termination signal when a last one of said predetermined number of cycles of said clock signal is counted;

detecting and replacing defective memory cells in said memory unit while said counter counts said predetermined number of cycles of said clock signal and until said count termination signal is generated by said counter, said step of detecting and replacing including;

setting each of said plurality of memory cells in said memory unit to a predetermined value;

reading out a stored value from each of said plurality of memory cells;

determining if said stored value and said predetermined value coincide for each of said plurality of memory cells;

recording said column number associated with each one of said plurality of memory cells where said stored value and said predetermined value do not coincide;

storing in said register one of said column numbers recorded in said recording step;

replacing said column identified by said register with said spare column; and

executing said second part of said startup sequence only after said count termination signal has been generated regardless of whether a defective memory cell was identified in said detecting and replacing step.

18. In a data processor having memory unit, a counter, and a register, said memory unit including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, said plurality of rows including a spare row and said plurality of columns including a spare column, and said plurality of rows having row addresses associated therewith, a method for automatically detecting and replacing defective memory cells in said memory unit upon startup comprising the steps of:

asserting a reset signal to indicate startup of said data processor;

executing a startup sequence in response to said reset signal, said startup sequence having a first part and a second part and including the steps of;

initializing said counter to count a predetermined number of cycles of said clock signal, wherein said predetermined number of cycles of said clock signal corresponds to said first part of said startup sequence;

generating a clock termination signal when a last one of said predetermined number of clock cycles of said clock signal is counted;

detecting and replacing defective memory cells in said memory unit while said counter counts said predetermined number of cycles of said clock signal and until said count termination signal is generated by said counter, said step of detecting and replacing including;

setting each of said plurality of memory cells in said memory unit to a predetermined value;

selecting one of said plurality of rows of said memory unit;

reading out a stored value from each of said plurality of memory cells in said row;

determining if said stored value and said predetermined value coincide for each of said plurality of memory cells in said row;

storing in said register said row address of a said row if said stored value and said predetermined value do not coincide for any one of said plurality of memory cells in said row;

inhibiting future access to said row if said stored value and said predetermined value do not coincide for any one of said plurality of memory cells in said row;

repeating steps for each of said plurality of rows until all of said plurality of rows of said memory unit have been tested; and

replacing, after said step of repeating, said row finally identified by said register with said spare row; and

executing said second part of said startup sequence only after said count termination signal has been generated regardless of whether a defective memory cell was identified in said detecting and replacing step.