Battery cell having an internal circuit for controlling its operation

• US 5,645,949 A
• Filed: 06/07/1995
• Issued: 07/08/1997
• Est. Priority Date: 09/12/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Young, Steven J.
• Primary Examiner(s): Kalafut, Stephen
• Assistant Examiner(s): CHANEY, CAROL DIANE
• Application Number:
  US08/482,950
• Time in Patent Office: 762 Days
• Field of Search: 429/7, 429/49, 429/61, 429/62, 320/21, 320/27, 320/37, 320/38, 320/35
• US Class Current: 429/7
• CPC Class Codes: G01R 31/006 on road vehicles, e.g. automobiles or trucks testing of ignition installations peculiar to internal combustion engines F02P17/00
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H01M 10/486 for measuring temperature
• CPC Class Codes: H01M 6/42 Grouping of primary cells into batteries H01M6/40 takes precedence
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/0018 using separate charge circuits
• CPC Class Codes: H02J 7/0036 using connection detecting circuits H02J7/0034 takes precedence
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A battery cell having a positive terminal, a negative terminal and a power producing core section (e.g., electrolyte) for systems, such as computer systems, cellular phones, etc. The battery cell also includes an internal circuit to monitor the state of the battery cell. The state that is monitored may include the temperature, charge level of the battery core section, the discharge/charge rate. The circuit may control the battery cell (e.g., cause charging of the battery cell). This internal circuit may be an integrated circuit, such as a microprocessor.

Claims

1. A battery cell comprising:

a positive terminal;

a negative terminal;

a battery cell core coupled to the negative terminal and positive terminal to provide power externally using the positive terminal and the negative terminal;

a processor coupled to the battery cell core, wherein the processor is programmed to internally monitor the battery cell state and internally control operation of the battery cell by executing a series of instructions; and

a charging device coupled to the battery cell core to charge the battery cell core.

2. The battery cell defined in claim 1 wherein the processor determines when the charging device is to charge the battery cell core.

3. The battery cell defined in claim 2 wherein the processor monitors charge rate and discharge rate of the battery cell core to determine when the charging device is to charge the battery cell.

4. The battery cell defined in claim 1 wherein the charging device comprises a transistor.

5. The battery cell defined in claim 1 further comprising a communications mechanism to transfer communications between the processor and a location external to the battery.

6. The battery cell defined in claim 5 wherein the communications mechanism comprises a wire bus.

7. The battery cell defined in claim 5 wherein the processor is programmed by downloading software to the processor from the location external to the battery using the communications mechanism.

8. The battery cell defined in claim 7 wherein the processor is programmed to stop the charging device from charging the battery cell core when the battery cell is being charged by an external charger.

9. The battery cell defined in claim 1 wherein the processor is programmed to monitor the battery cell core and to stop the charging device from charging the battery cell core in order to obtain maximum battery life.

10. The battery cell defined in claim 9 wherein the processor records charge/discharge cycles of the battery cell core to determine battery life.

11. A battery cell comprising:

a positive terminal;

a negative terminal;

a battery cell core coupled to the negative terminal and the positive terminal to provide power therefrom;

a processor coupled to the battery cell core and the charging mechanism to internally monitor state of the battery cell and internally control operation of the battery cell;

a charging mechanism coupled to the battery cell core to charge the battery cell core; and

wherein the processor determines when to charge the battery cell at which time the processor generates a signal causing the charging mechanism to charge the battery cell core.

12. The battery cell defined in claim 11 where the control circuit determines when to stop charging the battery cell, wherein the control circuit disables the charging mechanism after determining that charging of the battery cell is to stop.

13. The battery cell defined in claim 11 wherein the charging mechanism comprises a transistor.

14. The battery cell defined in claim 11 further comprising a communications mechanism to transfer communications between the processor and a location external to the battery.

15. The battery cell defined in claim 14 wherein the communications mechanism comprises a wire bus.

16. The battery cell defined in claim 14 wherein the processor is programmed by downloading software to the processor from the location external to the battery using the communications mechanism.

17. The battery cell defined in claim 16 wherein the processor is programmed to stop the charging mechanism from charging the battery cell core when the battery cell is being charged by an external charger.

18. The battery cell defined in claim 11 wherein the processor is programmed to monitor the battery cell core and to stop the charging mechanism from charging the battery cell core in order to obtain maximum battery life.

19. The battery cell defined in claim 18 wherein the processor records charge/discharge cycles of the battery cell core to determine battery life.

20. A system comprising:

a plurality of electronic devices coupled together to provide at least one function;

a battery pack coupled to provide power to the plurality of electronic devices, wherein the battery pack comprises a plurality of battery cells, wherein each of the plurality of battery cells comprises;

a positive terminal;

a negative terminal;

a battery cell core coupled to the negative terminal and the positive terminal to provide power externally therefrom using the positive terminal and the negative terminal; and

a processor coupled to the battery cell core to internally monitor the battery cell state and internally control operation of the battery cell.

21. The system defined in claim 20 wherein said each of the plurality of battery cells further comprises an internal communication bus to transfer information between said each of the plurality of battery cells and at least one of the plurality of electronic devices.

22. The system defined in claim 21 wherein said one of the plurality of electronic devices obtains state information from at least one of the plurality of battery cells and programs a portion of its processor based on the state information.

23. The system defined in claim 21 wherein the processor is programmed by downloading software to the processor from the location external to the battery using the communications mechanism.

24. The system defined in claim 23 wherein the processor is programmed not to charge the battery cell core when the battery cell is being charged by an external charger.

25. The system defined in claim 20 wherein at least one of the plurality of batteries comprises an internal charger and further wherein the processor is programmed to monitor the battery cell core and to stop the internal charger from charging the battery cell core in order to obtain maximum battery life.

26. The system defined in claim 25, wherein the processor records charge/discharge cycles of the battery cell core to determine battery life.