Printed circuit board with an integrated twisted pair conductor

• US 5,646,368 A
• Filed: 11/30/1995
• Issued: 07/08/1997
• Est. Priority Date: 11/30/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Parker, Gary, Muyshondt, Jorge Enrique, Wilkie, Bruce James
• Primary Examiner(s): Thomas, Laura
• Application Number:
  US08/565,373
• Time in Patent Office: 586 Days
• Field of Search: 174/33, 174/34, 174/261, 174/262, 174/250, 333/1, 333/4, 333/238, 333/245
• US Class Current: 174/33
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 2201/097 Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components

Abstract

A multi-layered printed circuit board having an integrated twisted pair conductor. In a preferred embodiment, the printed circuit board comprises two segmented conductor traces on a first and a second layer of the printed circuit board crisscrossing each other and a plurality of vias. The two segmented conductor traces on the first layer are connected to the two segmented conductor traces on the second layer through the vias. The twisted pair conductor may be shielded by adding a ground trace on either side of the conductor traces and a ground plane both above and below the conductor traces. The conductor traces may also be tuned to specific electrical characteristics by properly spacing the plurality of vias such that a specific number of turns per unit length are achieved. The continuous conductor traces may be further tuned by using a specific dielectric thickness as well as by designing the conductor traces to be of a specific dimension.

Claims

1. A printed circuit board having a first and a second layer comprising:

at least two segmented conductor traces on the first and on the second layer crisscrossing each other;

a plurality of vias for connecting the at least two segmented conductor traces on the first layer to the at least two segmented traces on the second layer to form two continuous conductor traces;

a first ground plane atop the first layer and a second ground plane below the second layer; and

a continuous ground trace on either side of said two continuous conductor traces for shielding said traces.

2. The printed circuit board of claim 1 further having a plurality of vias on either side of said two continuous traces for connecting said first ground plane to said second ground plane and to said ground traces on either side of said continuous traces.

3. A multi-layered printed circuit board for mounting and interconnecting a first and a second electronic component comprising:

means for mounting the first and the second electronic components;

means for interconnecting the first and the second electronic component including;

at least two segmented conductor traces on a first and on a second layer crisscrossing each other;

a plurality of vias for connecting the at least two segmented conductor traces on the first layer to the at least two segmented traces on the second layer to form two continuous conductor traces;

a first ground plane atop the first layer and a second ground plane below the second layer; and

a continuous ground trace on either side of said two continuous conductor traces for shielding said traces.

4. The multi-layered printed circuit board of claim 3 further having a plurality of vias on either side of said two continuous traces for connecting said first ground plane to said second ground plane and to said ground traces on either side of said continuous traces.

5. The multi-layered printed circuit board of claim 4 further comprising a differential receiver coupled to the conductor traces and to the first electronic component to filter out noise signals collected by the conductor traces.

6. A method of fabricating a twisted pair conductor within a multi-layered printed circuit board comprising the steps of:

crisscrossing at least two segmented conductor traces on a first and on a second layer of the printed circuit board; and

connecting the at least two segmented conductor traces on the first layer to the at least two segmented conductor traces on the second layer through a plurality of vies to form two continuous conductor traces;

placing a first ground plane atop the first layer and a second ground plane below the second layer; and

placing a continuous ground trace on either side of said two continuous conductor traces for shielding said traces.

7. The method of claim 6 further comprising the step of placing a plurality of vias on either side of said two continuous traces for connecting said first ground plane to said second ground plane and to said ground traces on either side of said continuous traces.

8. The method of claim 7 further comprising the step of adding a differential receiver at the end of the conductor traces to filter out noise signals.