Semiconductor thin film formed on a supporting substrate

• US 5,646,432 A
• Filed: 05/05/1993
• Issued: 07/08/1997
• Est. Priority Date: 05/14/1992
• Status: Expired due to Term

• Current Assignee: Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Matsushita, Katsuki, Senbonmatsu, Shigeru, Iwaki, Tadao, Takano, Ryuichi, Yamazaki, Tsuneo
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/057,987
• Time in Patent Office: 1,525 Days
• Field of Search: 257/347, 257/352, 257/431, 257/432, 257/458, 257/461, 257/752, 257/506, 257/353, 257/507, 257/753, 257/749
• US Class Current: 257/347
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/105 single crystal Si
• CPC Class Codes: G06E 3/003 forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integrals; for analysis or synthesis of functions using orthogonal functions
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor substrate is provided which has a semiconductor on insulator structure but in which can be formed a thin film integrated circuit having electrical characteristics and microstructure equal to or of greater density than a silicon integrated circuit formed using a bulk single crystal silicon wafer. The semiconductor substrate has a structure which is formed of a sequentially layered single crystal silicon thin film sandwiched between a thermally oxidized silicon film and a silicon oxide or silicon nitride film, an element smoothing layer, a fluoro-epoxy series resin adhesive layer, and a supporting substrate. The single crystal silicon thin film can have integrated circuit devices formed in a sub-micron geometry similar to that of a bulk single crystal silicon. A transparent glass or a bulk single crystal silicon wafer can be used as a supporting substrate. Therefore the semiconductor thin film can integrate a highly fine, dense and compact semiconductor integrated circuit or semiconductor optical element. The semiconductor thin film element has a transparent optical detection region or optical modulation region with 100 million pixels or more.

Claims

1. A semiconductor substrate comprising:

a single crystal semiconductor thin film layer having an element region which includes at least a portion of a first surface thereof;

an element smoothing layer formed on the element region of the single crystal semiconductor thin film layer; and

a supporting substrate laminated to the element smoothing layer by a resin adhesive layer such that a rough surface formed by a circuit element formed on the first surface of the single crystal semiconductor thin film layer is smoothed by the element smoothing layer to avoid separation of the semiconductor thin film layer and the supporting substrate.

2. A semiconductor substrate according to claim 1;

further comprising an insulating layer formed between the element smoothing layer and the single crystal semiconductor thin film layer to release an internal stress in the single crystal semiconductor thin film layer for protecting a circuit element formed thereon; and

a silicon oxide layer formed on a surface of the single crystal silicon thin film layer at the opposite side of the insulating layer.

3. A semiconductor substrate according to claim 1;

wherein the supporting substrate comprises a single crystal silicon substrate.

4. A semiconductor substrate according to claim 1;

wherein the supporting substrate comprises a glass substrate.

5. A semiconductor substrate according to claim 1;

wherein the resin adhesive layer comprises a material selected from an imide type resin and an epoxy type resin.

6. A semiconductor substrate according to claim 5;

wherein the resin adhesive layer includes fluorine.

7. A semiconductor substrate according to claim 1;

wherein the element smoothing layer comprises a silicon oxide film.

8. A semiconductor substrate according to claim 1;

wherein the element smoothing layer comprises a material selected from an imide type resin and an epoxy type resin.

9. A semiconductor substrate according to claim 1;

wherein the resin adhesive has a Shore hardness of at least 80.

10. A semiconductor substrate according to claim 1;

wherein the resin adhesive layer includes a plurality of dispersed fine particles.

11. A semiconductor substrate according to claim 1;

wherein the difference in linear coefficient of expansion between the supporting substrate and the single crystal semiconductor thin film layer is less than 1.5×

10^-6 /°

C.

12. A semiconductor substrate according to claim 1;

further comprising an insulated gate field effect transistor having a source region and a drain region formed in the element region of the single crystal semiconductor thin film layer, a channel region formed in the element region of the single crystal semiconductor thin film layer between the source region and the drain region, an insulating film formed over the channel region, and a gate electrode formed over the insulating film.

13. A semiconductor substrate according to claim 1;

further comprising an optical detecting element comprising a PN junction formed in the element region of the single crystal semiconductor thin film layer.

14. A semiconductor substrate according to claim 13;

wherein the optical detecting element includes a PIN type junction comprising a P-type region formed in the element region of the single crystal semiconductor thin film layer, an I-type region interfacing with the P-type region, and an N-type region interfacing with the I-type region.

15. A semiconductor substrate according to claim 1;

further comprising a second semiconductor thin film layer having a second element region which includes at least a portion of a first surface thereof, and a second element smoothing layer formed on the second element region of the second semiconductor thin film layer, the second semiconductor thin film layer and the second element smoothing layer being formed between the resin adhesive layer and the single crystal semiconductor thin film layer such that a rough surface formed by a second circuit element formed in the first surface of the second semiconductor thin film layer is smoothed by the second element smoothing layer to avoid separation of the single crystal semiconductor thin film layer, the second semiconductor thin film layer, and the supporting substrate.

16. A semiconductor substrate according to claim 15;

wherein the second circuit element formed in the second semiconductor thin film layer is electrically connected to the circuit element formed on the single crystal semiconductor thin film layer through a joint hole formed in the second element smoothing layer and the resin adhesive layer.

40. A semiconductor substrate according to claim 1;

further comprising a second element region which includes at least a portion of a first surface of the supporting substrate, and a second element smoothing layer formed between the resin adhesive layer and the first surface of the supporting substrate to smooth a rough surface formed by a circuit element formed in the second element region of the supporting substrate to avoid separation between the supporting substrate and the single crystal semiconductor thin film layer.

41. A semiconductor substrate according to claim 40;

wherein a first circuit element formed in the element region of the single crystal semiconductor thin film layer is electrically connected to a second circuit element formed in the second element region of the supporting substrate through a joint hole formed in the resin adhesive layer and the second element smoothing layer.

17. A liquid crystal light valve comprising:

a drive substrate having a drive electrode and a drive circuit for electrically exciting the drive electrode;

an opposite substrate opposing the drive substrate; and

a liquid crystal layer formed between the drive substrate and the opposite substrate;

wherein the drive substrate comprises a single crystal semiconductor thin film layer, an element smoothing layer formed on the single crystal semiconductor thin film layer, a supporting substrate laminated on the element smoothing layer by a resin adhesive layer and a semiconductor circuit element formed in a surface of the single crystal semiconductor thin film layer contacting the element smoothing layer, such that the element smoothing layer is effective to smooth a rough surface formed by the semiconductor circuit element to avoid separation of the semiconductor thin film layer and the supporting substrate; and

wherein the drive circuit comprised of the semiconductor circuit element and the drive electrode is arranged integrally on the single crystal semiconductor thin film layer, whereby an optical transmittance through the light valve is controlled by applying a voltage across the liquid crystal layer when the drive electrode is electrically excited by the drive circuit.

18. A liquid crystal light valve according to claim 17;

wherein the resin adhesive layer comprises a material selected from an imide type resin and an epoxy type resin.

19. A liquid crystal light valve according to claim 17;

wherein the drive circuit includes a plurality of drive elements arranged in a matrix form, the drive electrode is formed of a plurality of pixel electrodes arranged in a matrix form, and wherein respective pixel electrodes are selectively excited by corresponding ones of the drive elements.

20. A semiconductor optical detector comprising:

a semiconductor optical detecting element; and

a drive electrode connected to and exciting the semiconductor optical detecting element in accordance with a predetermined signal;

wherein the semiconductor optical detecting element and the drive electrode are formed in a drive substrate comprising a single crystal semiconductor thin film bonded to a supporting substrate;

the semiconductor optical detecting element being formed in the single crystal semiconductor thin film, and the drive electrode being formed integrally on the single crystal semiconductor thin film, whereby an optical detection signal is controlled by activating the optical detecting element when the drive electrode is excited by a drive circuit.

21. A semiconductor optical detector according to claim 20;

wherein the optical detecting element is arranged in a matrix form and comprises a plurality of silicon photodiodes, the drive electrode comprises a plurality of corresponding drive electrodes, and the drive circuit includes means for scanning and detecting optical detection signals from the silicon photodiodes.

22. A semiconductor substrate comprising:

a semiconductor thin film having a first device region;

a smoothing layer formed on the semiconductor thin film and contacting the first device region to smooth a rough surface formed by a circuit element formed in the first device region; and

a supporting substrate laminated to the smoothing layer by an adhesive layer such that separation of the semiconductor thin film and the supporting substrate is prevented by the smoothing layer.

23. A semiconductor substrate according to claim 22;

further comprising an insulation layer formed between the smoothing layer and the semiconductor thin film effective to release an internal stress in the semiconductor thin film for protecting the first device region.

24. A semiconductor substrate according to claim 22;

wherein the supporting substrate comprises single crystal silicon.

25. A semiconductor substrate according to claim 22;

wherein the supporting substrate comprises a transparent material.

26. A semiconductor substrate according to claim 25;

wherein the transparent material comprises glass.

27. A semiconductor substrate according to claim 25;

wherein the transparent material comprises quartz.

28. A semiconductor substrate according to claim 22;

wherein the adhesive layer comprises a material selected from an imide type resin and an epoxy type resin.

29. A semiconductor substrate according to claim 22;

wherein the adhesive layer includes fluorine.

30. A semiconductor substrate according to claim 22;

wherein the smoothing layer comprises a silicon dioxide film.

31. A semiconductor substrate according to claim 22;

wherein the smoothing layer comprises a material selected from an imide type resin and an epoxy type resin.

32. A semiconductor substrate according to claim 22;

wherein the adhesive has a Shore hardness of at least 80.

33. A semiconductor substrate according to claim 22;

wherein the adhesive layer includes fine particles dispersed throughout.

34. A semiconductor substrate according to claim 22;

wherein the difference in linear coefficient of expansion between the supporting substrate and the semiconductor thin film is less than 1.5×

10^-6 /°

C.

35. A semiconductor substrate according to claim 22;

further including an insulated gate field effect transistor having a source region and a drain region formed in the first device region of the semiconductor thin film, a channel region formed between the source region and the drain region, and a gate electrode formed over the channel region.

36. A semiconductor substrate according to claim 22;

further including an optical detecting element comprising a PN junction formed in the first device region of the semiconductor thin film.

37. A semiconductor substrate according to claim 36;

wherein the optical detecting element includes a PIN type junction comprising a P-type region formed in the semiconductor thin film, an I-type region interfacing with the P-type region, and an N-type region interfacing with the I-type region.

38. A semiconductor substrate according to claim 36;

further comprising a second smoothing layer formed between the adhesive layer and the supporting substrate; and

a second device region formed in a surface of the supporting substrate contacting the second smoothing layer.

39. A semiconductor substrate according to claim 38;

wherein the second device region formed in the supporting substrate is electrically connected to the first device region formed in the semiconductor thin film through a joint hole formed in the second smoothing layer and the adhesive layer.

42. A semiconductor substrate comprising:

a first semiconductor thin film layer having a first element region which includes at least a portion of a first surface thereof;

a first element smoothing layer formed over the first element region;

a second semiconductor thin film layer having a second element region which includes at least a portion of a first surface thereof;

a second element smoothing layer formed over the second element region;

a first adhesive film layer for bonding the first semiconductor thin film layer and the first element smoothing layer to the second semiconductor thin film layer and the second element smoothing layer to form a multilayer circuit; and

a supporting substrate bonded to the multilayer circuit by a second adhesive layer;

wherein the first element smoothing layer is effective to smooth a rough surface formed by a circuit element formed in the first element region of the first semiconductor thin film, and the second element smoothing layer is effective to smooth a rough surface formed by a circuit element formed in the second element region of the second semiconductor thin film to thereby avoid separation of the first and second semiconductor thin film layers and the supporting substrate.

43. A semiconductor substrate comprising:

a semiconductor thin film layer having a first element region which includes at least a first surface thereof;

a first element smoothing layer formed on the first element region;

a supporting substrate for supporting the semiconductor thin film layer; and

an adhesive layer for bonding the supporting substrate and the semiconductor thin film layer on the side having the first element smoothing layer;

wherein the first element smoothing layer is effective to smooth a rough surface caused by a circuit element formed in the first element region to avoid separation of the semiconductor thin film layer and the supporting substrate.

44. A semiconductor substrate according to claim 43;

wherein the semiconductor thin film layer comprises a single crystal silicon thin film layer.

45. A semiconductor substrate according to claim 43;

wherein the semiconductor thin film layer comprises a thinned single crystal silicon wafer.

46. A semiconductor substrate according to claim 43;

further comprising a first insulating layer formed between the first element smoothing layer and the first surface of the semiconductor thin film layer to release an internal stress in the semiconductor thin film layer for protecting a circuit element formed in the element region.

47. A semiconductor substrate according to claim 46;

further comprising a second insulating layer formed on a second surface of the semiconductor thin film opposite the first surface.

48. A semiconductor substrate according to claim 43;

further comprising a second element region formed in the supporting substrate and including at least a portion of a first surface thereof, and a second element smoothing layer formed between the adhesive layer and the first surface of the supporting substrate to smooth a rough surface caused by a circuit element formed in the second element region of the supporting substrate to prevent separation of the semiconductor thin film layer and the supporting substrate.

49. A semiconductor substrate according to claim 48;

wherein a circuit element formed in the first element region of the semiconductor thin film layer is electrically connected to a circuit element formed in the second element region of the supporting substrate through a joint hole formed in the second element smoothing layer and the adhesive layer.