System and method for dynamically reconfiguring a programmable gate array

• US 5,646,544 A
• Filed: 06/05/1995
• Issued: 07/08/1997
• Est. Priority Date: 06/05/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Iadanza, Joseph Andrew
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/462,392
• Time in Patent Office: 764 Days
• Field of Search: 326/40, 326/41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

In each of multiple logic cells of a Programmable Gate Array ("PGA"), a programing array is provided having multiple programming words therein. Each of the programming words is engagable to control the configuration of the logic cell. The programming words are selectively engaged such that multiple functions are performed by the logic cell within the PGA. As a result, a PGA with a number of virtual logic cells in excess of actual physical logic cells is provided. The PGA therefore has the capability to emulate a PGA with a larger number of logic cells than it physically has.

Claims

1. A configuration system for a logic cell within a programmable array, comprising:

a plurality of programming words simultaneously stored in said programmable array, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell, including a wordline for each of said at least two programming words to selectively engage the respective programming word;

wherein said means to engage further includes means for coupling the wordlines to selected logic cells within the programmable array to facilitate engagement of the selected programming word by said selected logic cells.

2. A configuration system for a logic cell within a programmable array, comprising:

a plurality of programming words simultaneously stored in said programmable array, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell;

wherein said means to engage comprises a programmable counter for sequentially engaging different programming words of said at least two programming words.

3. The configuration system of claim 2, wherein said programmable counter comprises at least one other logic cell of the programmable array.

4. The configuration system of claim 2, wherein said programmable counter comprises means for sequentially engaging each programming word of said at least two programming words as said selected programming word.

5. The configuration system of claim 2, wherein said programmable counter comprises means for repeatedly sequentially engaging the individual words of a preprogrammed subset of programming words of said at least two programming words as said selected programming word.

6. The configuration system of claim 2, wherein said programmable counter comprises a common programmable counter to said logic cell and to other logic cells within said programmable array.

7. The configuration system of claim 2, wherein said programmable counter is only utilized by said logic cell of all logic cells within said programmable array.

8. An integrated circuit chip having a logic cell therein, said logic cell comprising:

a plurality of programming words simultaneously stored in the logic cell, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell;

wherein said integrated circuit chip further comprises an Application Specific Integrated Circuit macro or a microprocessor macro.

9. A configuration system for a logic cell within a programmable array, comprising:

a plurality of programming words simultaneously stored in said programmable array, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell;

wherein said means to engage comprises at least one other logic cell within said programmable array.

10. A configuration system for a logic cell within a programmable array, comprising:

a plurality of programming words simultaneously stored in said programmable array, of which each of at least two programming words is engagable to control a configuration of the logic cell;

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell; and

means for writing to a different programming word than said selected programming word, while said logic cell remains operational using said selected programming word.

11. The configuration system of claim 10, wherein said means for writing comprises a dual-ported memory including said at least two programming words.

12. A method for configuring a logic cell within a programmable array, said logic cell being controllable by each programming word of at least two of a plurality of programming words associated with said logic cell and simultaneously stored in said PA, said method comprising:

determining a selected programming word of said at least two programming words;

engaging said selected programming word to control the configuration of the logic cell; and

writing to a different programming word than said selected programming word, while said logic cell remains operational using said selected programming word.

13. The method of claim 12, wherein said logic cell includes a dual-ported memory including said at least two programming words, and wherein said writing comprises writing a new programming word to said dual-ported memory while simultaneously reading said selected programming word therefrom.

14. A method for configuring a logic cell within a programmable array, said logic cell being controllable by each of at least two programming words of a plurality of programming words associated with said logic cell and simultaneously stored in said programmable array, said method comprising:

determining a sequence of selected programming words of said at least two programming words;

engaging said sequence of selected programming words to sequentially control the configuration of the logic cell; and

sequentially engaging the programming words of said at least two programming words as said sequence of selected programming words.

15. A method for configuring a logic cell within a programmable array, said logic cell being controllable by each of at least two programming words of a plurality of programming words associated with said logic cell and simultaneously stored in said programmable array, said method comprising:

determining a sequence of selected programming words of said at least two programming words;

engaging said sequence of selected programming words to sequentially control the configuration of the logic cell; and

repeatedly sequentially engaging the individual words of a preprogrammed subset of programming words of said at least two programming words as said sequence of selected programming words.

16. A logic cell comprising:

a plurality of programming words simultaneously stored within the logic cell, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said at least two programming words to control the configuration of the logic cell;

wherein said means to engage includes a programmable counter for engaging the individual words of a preprogrammed sequence of said at least two programming words as said selected programming word.

17. An integrated circuit chip having a logic cell therein, said logic cell comprising:

a plurality of programming words simultaneously stored in the logic cell, of which each of at least two programming words is engagable to control a configuration of the logic cell; and

means to engage a selected programming word of said plurality of programming words to control the configuration of the logic cell;

wherein said means to engage includes a programmable counter for engaging the individual words of a preprogrammed sequence of said at least two programming words as said selected programming word.