Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device
First Claim
1. A sense amplifier circuit for differentially amplifying potentials on a first bit line and a second bit line paired with said first bit line, said first and second bit lines precharged at an intermediate potential between a first power potential and a second power potential different from said first power potential, said sense amplifier circuit comprising:
- a first activation transistor coupled between a first power node receiving said first power potential and a first node precharged to said intermediate potential and responsive to a first sense amplifier enable signal being active for electrically coupling said first power node and said first node;
a first sense transistor connected between said first node and said first bit line and having a gate coupled to said second bit line and having a backgate receiving a first backgate potential precharged to a first precharge potential prior to activation of said first sense amplifier enable signal and changing with a potential at said first node during activation of said first sense amplifier enable signal, a difference in absolute value between said first precharge potential and said first power potential being greater than that between said intermediate potential and said first power potential; and
a second sense transistor connected between said first node and said second bit line and having a gate coupled to said first bit line and a backgate receiving said first backgate potential.
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Accused Products
Abstract
N channel sense amplifier transistors have their backgate potentials set to a backgate precharge potential higher than a potential intermediate between an operation power supply potential and a ground potential prior to start of sensing operation, and then lowered following the lowering of an n common source node potential during the sensing operation. The n common source node is precharged to the intermediate potential. The backgate precharge potential is set no greater than a potential of the intermediate potential plus a pn junction diffusion, to suppress a leakage current from the backgate to source or drain of each of the sense amplifier transistors. P channel sense amplifier transistors have also their backgate potential set to a precharge potential lower than the intermediate potential prior to sensing operation and raised following the rise of a p common source node potential.
255 Citations
31 Claims
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1. A sense amplifier circuit for differentially amplifying potentials on a first bit line and a second bit line paired with said first bit line, said first and second bit lines precharged at an intermediate potential between a first power potential and a second power potential different from said first power potential, said sense amplifier circuit comprising:
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a first activation transistor coupled between a first power node receiving said first power potential and a first node precharged to said intermediate potential and responsive to a first sense amplifier enable signal being active for electrically coupling said first power node and said first node; a first sense transistor connected between said first node and said first bit line and having a gate coupled to said second bit line and having a backgate receiving a first backgate potential precharged to a first precharge potential prior to activation of said first sense amplifier enable signal and changing with a potential at said first node during activation of said first sense amplifier enable signal, a difference in absolute value between said first precharge potential and said first power potential being greater than that between said intermediate potential and said first power potential; and a second sense transistor connected between said first node and said second bit line and having a gate coupled to said first bit line and a backgate receiving said first backgate potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor memory device comprising:
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a first and second bit lines each connecting a predetermined number of memory cells; a sense amplifier including a first sense transistor coupled between a first node and said first bit line and having a control gate coupled to said second bit line and a first backgate, and a second sense transistor coupled between said first node and said second bit line and having a control gate coupled to said first bit line and a second backgate, said first and second backgates connected to a first backgate node, for differentially amplifying potentials on said first and second bit lines; a first sense enable transistor coupled between a first power node and said first node and responsive to a first sense amplifier enable signal being active for electrically connecting said first power node and said first node; precharge circuitry coupled to said first node for precharging said first node at an intermediate potential between a first power potential and a second power potential different from said first power potential in response to a precharge instructing signal being active; first backgate potential generator operating with said first and second power potentials for generating a first backgate precharge potential at a level between said intermediate potential and said second power potential; a first means coupled between said first backgate potential generator and said first backgate node for transmitting said first backgate precharge potential onto said first backgate node in response to a first control signal being active; a second means coupled between said first node and said first backgate node for electrically connecting said first node and said first backgate node in response to a second control signal being active; and controller coupled to receive a memory cycle start instructing signal and responsive to activation of said memory cycle start instructing signal for activating said first control signal for application to said first means prior to activation of said first sense amplifier enable signal, and for activating said second control signal during activation of said first sense amplifier enable signal, said precharge instructing signal being deactivated in response to activation of said memory cycle start instruct signal, and said first sense amplifier enable signal being activated in response to the activation of said memory cycle start instructing signal. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification