CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

• US 5,646,901 A
• Filed: 03/26/1996
• Issued: 07/08/1997
• Est. Priority Date: 03/26/1996
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Jonathan, Sharpe-Geisler, Bradley A., Barsan, Radu
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/625,403
• Time in Patent Office: 469 Days
• Field of Search: 365/185, 365/149, 365/189, 365/230.01, 365/184, 365/218
• US Class Current: 365/218
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.

Claims

1. A CMOS memory cell comprising:

a common floating gate;

a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;

an output node;

an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;

a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and

a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.

2. The CMOS memory cell of claim 1, wherein the pass gate is an NMOS transistor.

3. The CMOS memory cell of claim 1, wherein the output node is further connected to the drain of the PMOS transistor.

4. The CMOS memory cell of claim 1, wherein the NMOS transistor is a depletion mode transistor having a threshold below zero volts.

5. A CMOS memory cell comprising:

a common floating gate;

a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;

an output node;

an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;

a PMOS transistor having a drain connected to the drain of the NMOS transistor, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel.

6. A method of programming a first CMOS memory cell including a common floating gate;

a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate;

an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and

a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein programming results in electrons being added to the common floating gate, programming comprising the steps of;

applying a first voltage difference between the ACG node and the WCL node so that electrons transfer from the source of the NMOS transistor to the common floating gate; and

applying a second voltage difference, concurrent with application of the first voltage difference, between the ACG node and the WCH node so that substantially no tunneling of electrons occurs from the source of the PMOS transistor to the common floating gate.

7. The method of claim 6 further comprising a step for preventing current leakage in second CMOS memory cells having components similar to the first CMOS memory cell, with capacitors of the second CMOS memory cells having ACG nodes connected to the ACG node of the first CMOS memory cell, the further step comprising:

applying a third voltage difference between the ACG node and the WCL node of the second memory cells, the third voltage difference being less than the first voltage difference so that substantially no electrons transfer from the source of the NMOS transistor to the common floating gate of the second CMOS memory cells.

8. The method of claim 7, wherein the third voltage difference is a minimum reliable voltage difference which will substantially prevent electrons from transferring from the source of the NMOS transistor to the common floating gate of the second CMOS memory cells.

9. The method of claim 7 further comprising a step for preventing current leakage in third CMOS memory cells having components similar to the first CMOS memory cell, with WCL lines of the third CMOS memory cells being connected to the WCL lines of the second CMOS memory cell, the further step comprising:

applying a fourth voltage difference between the ACG line and the WCL node of the second memory cells, the fourth voltage difference having a value set to prevent tunneling in the third CMOS memory cells.

10. The method of claim 6, wherein the source and drain of the PMOS transistor is provided in an n well of a p- type substrate, the n well being connected to an Nwell node, the method further comprising the step of:

applying a voltage potential to the Nwell node greater than a voltage potential provided to the WCH node during application of the second voltage difference.

11. The method of claim 9 further comprising steps for erasing the first, second and third CMOS memory cells, wherein erasing results in electrons being added to the common floating gate, the further steps comprising:

applying a fifth voltage difference between the ACG node and the WCH node of the first, second and third CMOS memory cells so that electrons transfer from the common floating gate to the source of the PMOS transistor in each CMOS memory cell; and

applying substantially no voltage difference between the WCL and WCH nodes of the first, second and third CMOS memory cells, concurrent with application of the fifth voltage difference, so that no substantial electron transfer occurs from the common floating gate to the source of the NMOS transistor in each CMOS memory cell.

12. The method of erasing a CMOS memory cell including a common floating gate;

a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate;

an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and

a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein erasing results in electrons being added to the common floating gate, erasing comprising the steps of;

applying a voltage difference between the ACG node and the WCH node of the CMOS memory cell so that electrons transfer from the common floating gate to the source of the PMOS transistor; and

applying substantially no voltage difference between the WCL and WCH nodes concurrent with application of the fifth voltage difference, so that no substantial electron transfer occurs from the common floating gate to the source of the NMOS transistor.

13. A programmable logic device (PLD) receiving an input, the PLD comprising:

a sense amplifier having a product term (PT) input and a product term ground (PTG) input;

a plurality of memory cells, each comprising;

a common floating gate;

a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;

an output node;

an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;

a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and

a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.