Method and apparatus for generating instructions for use in testing a microprocessor
First Claim
1. A method for selecting instructions for use in a process for generating dynamically-biased pseudo-random test patterns, the method comprising:
- providing an instruction list having a list identifier, an instruction set having at least one instruction, a pick value, and an instruction selection discipline value;
selecting an instruction from the instruction set based on the selection discipline value, wherein the discipline value specifies a manner of selecting; and
repeating the step of selecting based on the pick value.
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Accused Products
Abstract
An apparatus and method for generating pseudo-random test instructions for testing a microprocessor begins by providing an array of list structures (502 through 508). Each list structure (502 through 508) contains a list of instructions, a discipline field (34), a pick field (42) and a biasing field (36). A random list of instructions is created by using a list selection discipline field to determine which list (502 through 508) is selected. The discipline field in the particular list (502 through 508) is then used to determine a manner in which instructions are selected from a list of instructions contained within the list structure. The pick field indicates how many instructions are to be selected from each selected list structure using a method determined via the discipline field. Once a number of instructions equal to the pick value has been selected, another list structure is selected as determined in the list selection discipline field until an entire test file of computer instructions is fully generated.
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Citations
31 Claims
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1. A method for selecting instructions for use in a process for generating dynamically-biased pseudo-random test patterns, the method comprising:
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providing an instruction list having a list identifier, an instruction set having at least one instruction, a pick value, and an instruction selection discipline value; selecting an instruction from the instruction set based on the selection discipline value, wherein the discipline value specifies a manner of selecting; and repeating the step of selecting based on the pick value. - View Dependent Claims (2, 3, 4, 5)
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6. A method for generating test instructions, the method comprising the steps of:
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(a) forming a plurality of instruction list structures in computer memory, each instruction list structure in the plurality of instruction list structures having a name field, a list containing at least one computer instruction, a discipline field for determining a manner for selecting computer instructions from the list containing at least one computer instruction, a pick field which indicates the number of instructions which are to be chosen from the list containing at least one computer instruction, and a bias field which defines a manner in which operands are to be generated for the computer instructions selected from the list containing at least one computer instruction; (b) selecting one list structure among the plurality of instruction list structures as a selected list structure; (c) selecting a selected computer instruction from the list containing at least one computer instruction which is within the selected list structure, the selecting being performed in accordance with the discipline field of the selected list structure; (d) determining additional information for the selected computer instruction in accordance with the bias field of the selected list structure; (e) repeating steps (c) through (e) until a proper number of selected instructions are processed in accordance with the pick field of the selected list structure; and (f) repeating steps (b) through (f) for another selected list structure until a termination condition is determined. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for generating dynamically-biased pseudo-random test patterns for execution by an execution device, the method comprising:
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(a) creating a plurality of instruction lists in computer memory, each instruction list in the plurality of instruction lists having a list identifier, an instruction set listing at least one computer instruction, a pick value, and an instruction selection discipline value; (b) selecting a selected instruction list from the plurality of instruction lists; (c) selecting an instruction from the instruction set of the selected instruction list based on the selection discipline value of the selected instruction list, wherein the discipline value specifies a manner of selecting; (d) repeating the steps (c)-(d) a number of times determined by the pick value of the selected instruction list to create a list of selected instructions in computer memory; and (e) repeating the steps (b)-(e) until a complete computer file of selected instructions exists in computer memory. - View Dependent Claims (18, 19)
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20. A data processor for generating test instructions used for testing a device under test, the data processor comprising:
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a central processing unit (CPU); and computer memory coupled to the central processing unit (CPU), the computer memory containing; an array of instruction list structures wherein each instruction list structure in the array of instruction list structures contains a list of instructions; a verification test generator which accesses the array of instruction list structures using a process defined by a list discipline field, the verification test generator choosing a plurality of instructions from at least one of the instruction list structures as a portion of the test instructions before another instruction list structure is chosen for processing; and an output test instruction file which is used to store the plurality of instructions chosen by the verification test generator. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A verification test generator comprising:
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means for creating a plurality of list structures; means for selecting a selected list structure from the plurality of list structures; and means for selecting two or more test instructions from the selected list structure and writing the two or more test instructions to a test instruction file before selecting another selected list structure to continue test instruction generation; and means for determining a discipline for selecting test instructions for each list structure in the plurality of list structures.
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29. A test instruction generator stored on computer readable medium, the test instruction generator comprising:
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a first plurality of computer instructions for creating a plurality of list structures, each list structure comprising a list containing at least one computer instruction, a discipline field for determining a manner for selecting computer instructions from the list containing at least one computer instruction, a pick field which indicates the number of instructions to be chosen from the list containing at least one computer instruction, and a bias field which is used to define a manner in which operands are to be generated for the computer instructions selected from the list containing at least one computer instruction; a second plurality of computer instructions for selecting a selected list structure from the plurality of list structures using a global discipline methodology; a third plurality of computer instructions for selecting two or more test instructions from the list of at least one computer instruction and writing the two or more test instructions to a test instruction file before selecting another selected list structure to continue test instruction generation; and a fourth plurality of computer instructions for applying assembled test instructions from the test instruction file to a device under test to test the device under test for proper operation.
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30. A data structure for allowing the creation of a data file containing test instructions for testing a CPU, the data structure comprising:
at least one list structure formed in computer memory wherein each list structure in the at least one list structures comprises; a list identifier field; a list of at least one test instruction which is selectable by an algorithm for inclusion in a test file used for testing an electrical device; a discipline field which indicates a manner in which the test instructions are to be selected from the list of at least one test instructions; a pick field which is used to indicate a number of test instructions to be sequentially selected from the list structure before another list structure is selected; and a bias field which indicates a manner in which operands are to be created for use in each test instructions selected from the list of at least one test instructions.
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31. A method for testing a microprocessor by generating and utilizing a sequence of pseudo random test instructions, the method comprising:
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providing an instruction list having a list identifier, an instruction set having at least one instruction, a pick value, a bias field, and a selection discipline value; selecting a number of selected instructions from the instruction set equal to the pick value, wherein the discipline value specifies a manner of selecting; generating operands for the selected instructions using the bias field; storing the selected instructions in a test file and storing the expected test results in a result file; executing of the number of instructions using an integrated circuit design file stored in memory to maintain a state of the machine for generating proper operands of subsequent test instructions; manufacturing a plurality of integrated circuits in accordance with the integrated circuit design file; and applying an executable embodiment of the test file to the plurality of integrated circuits to test the plurality of integrate circuit for proper operation by comparing actual test results to contents of the result file.
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Specification