DS/CDMA receiver for high-speed fading environment

• US 5,646,964 A
• Filed: 07/08/1994
• Issued: 07/08/1997
• Est. Priority Date: 07/08/1993
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yoshida, Shosei, Ushirokawa, Akihisa
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/272,689
• Time in Patent Office: 1,096 Days
• Field of Search: 375/200-208, 375/232, 375/233, 375/234, 375/260, 375/285, 375/326, 375/340, 375/344, 375/346, 375/348, 375/349, 375/350, 375/371, 455/50, 455/52.1, 455/52.3, 455/63, 455/65, 455/67.6, 455/296, 455/303, 455/304, 455/307, 370/18, 370/69.1, 370/93, 370/123
• US Class Current: 375/346
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/712 Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Abstract

A receiver is disclosed for a DS/CDMA communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier. The receiver includes an interference canceller for cancelling signals from undesired sources introduced to a signal received from a desired source using a feedback signal. A phase variation canceller is provided for cancelling a phase variation that occurs in an interval between successive symbols of the received signal. Both cancellers are connected in series. A decision circuit compares an input signal from the interference canceller or from the phase variation canceller with a threshold and produces an output representing one of two discrete values depending on whether it is higher or lower than the threshold. A correction circuit derives a correction signal from a signal produced by the interference canceller and applies it to the interference canceller as the feedback signal.

Claims

1. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a plurality of signal sources transmit DS/CDMA signals on a radio frequency carrier, each of the DS/CDMA signals being produced by spreading a symbol with a unique spread code at predetermined chip intervals, comprising:

receiver means having a spectral bandwidth for receiving said DS/CDMA signals;

an interference canceller for cancelling signals from desired sources introduced to a signal received by the receiver means from a desired source by using a feedback signal;

a phase variation canceller for cancelling a fading-related phase variation that occurs between successive symbols of the signal from the desired source;

decision means for comparing an input signal with a decision threshold and producing an output signal representing one of two discrete values depending on whether the input signal is higher or lower than the threshold, the interference canceller and the phase variation canceller being connected in series between said receiver means and said decision means for producing an interference- and phase-variation-cancelled signal, and

correction signal generator means for deriving a correction signal from said interference- and phase-variation cancelled signal and applying the correction signal to said interference canceller as said feedback signal,

wherein the interference canceller is a linear equalizer including;

a tapped-delay line having delay-line tap intervals equal to or smaller than said predetermined chip intervals;

a plurality of multipliers connected to successive taps of the delay line for multiplying tap signals on said successive taps with respective tap weight vectors;

an adder for summing outputs of the multipliers to produce a signal as an output signal of the interference canceller; and

a tap-weight controller for deriving said tap weight vectors respectively from correlations between said tap signals and said feedback signal, whereby the tap weight vectors are orthogonally oriented to the signals from the undesired sources.

2. A receiver as claimed in claim 1, wherein said phase variation canceller is connected to the output of said interference canceller and comprises:

delay means for introducing a delay corresponding to one symbol of said DS/CDMA signal into an output signal of said interference canceller; and

multiplier means for multiplying the output signal of said interference canceller with the signal delayed by said delay means.

3. A receiver as claimed in claim 2, wherein said phase variation canceller further comprises an automatic gain controlled amplifier connected to the output of said interference canceller for generating a constant amplitude signal and applying the constant amplitude signal to said delay means and said multiplier means.

4. A receiver as claimed in claim 2, wherein said phase variation canceller further comprises a normalizer connected between said delay means and said multiplier means.

5. A receiver as claimed in claim 1, wherein said correction signal generator means includes error detector means for detecting an error between the input and output signals of said decision means as said correction signal.

6. A receiver as claimed in claim 5, wherein said interference canceller further comprises a decision feedback equalizer which comprises;

a tapped-delay line for receiving the output signal of the decision means, the second tapped-delay line delay-line tap intervals equal to symbol intervals at which said symbol occurs;

a plurality of multipliers for multiplying tap signals of the tapped-delay line with respective tap weight vectors;

an adder for summing outputs of the multipliers to produce sum signal;

means for combining the sum signal with the output signal of the adder of the linear equalizer to produce a signal as an output signal of the interference canceller; and

a tap-weight controller for deriving the tap weight vectors of the second tapped-delay line respectively from correlations between the tap signals of the second tapped-delay line and the error detected by the error detector means.

7. A receiver as claimed in claim 1, wherein said phase variation canceller is connected between said interference canceller and said decision means, and comprises:

means for deriving a reference carrier from input and output signals of said decision means; and

means for synchronizing the output signal of said interference canceller to said reference carrier.

8. A receiver as claimed in claim 1, wherein said phase variation canceller is connected between said receiver means and said interference canceller and comprises:

means for deriving a reference carrier from input and output signals of said decision means; and

means for synchronizing the output signal of said receiver means to said reference carrier.

9. A receiver as claimed in claim 7 or 8, wherein said reference carrier deriving means comprises:

phase detector means for detecting a phase difference between the input and output signals of said decision means; and

integrator means for integrating said phase difference for producing said reference carrier.

10. A receiver as claimed in claim 7 or 8, wherein said synchronizing means comprises a phase shifter for shifting the output signal of said interference canceller according to said reference carrier.

11. A receiver as claimed in claim 7 or 8, wherein said synchronizing means comprises a phase shifter for shifting the output signal of said receiver means according to said reference carrier.

12. A receiver as claimed in claim 1, 2 or 8, wherein said interference canceller further comprises a decision feedback equalizer which comprises:

a tapped-delay line for receiving the output signal of the decision means, the second tapped-delay line delay-line tap intervals equal to symbol intervals at which said symbol occurs;

a plurality of multipliers for multiplying tap signals of the tapped-delay line with respective tap weight vectors;

an adder for summing outputs of the multipliers to produce a sum signal;

means for combining the sum signal with the output signal of the adder of the linear equalizer to produce a signal as an output signal of the interference canceller; and

a tap-weight controller for deriving the tap weight vectors of the second tapped-delay line respectively from correlations between the tap signals of the second tapped-delay lines and said feedback signal.

13. A receiver as claimed in claim 1, further comprising a matched filter connected between said receiver means and said interference canceller for despreading the signal received by the receiver means from said desired source according to said predetermined spread code.

14. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

a delay line connected to said receiver means, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

maximum ratio combiner means for weighting output signals of said interference cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

decision means for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold, and supplying the output signal of the decision means to said maximum ratio combiner means as said second feedback signal; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to each of said interference cancellers as said first feedback signal.

17. A receiver as claimed in claim 14, 15 or 16, wherein each of said interference cancellers comprises a linear equalizer for cancelling said components according to the error detected by said error detector means.

18. A receiver as claimed in claim 14, 15 or 16, wherein each of said interference cancellers comprises a decision feedback equalizer for cancelling said components according to the error detected by said error detector means and the output signal of said decision means.

15. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

a delay line connected to said receiver means, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a correction signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

a plurality of phase variation cancellers connected respectively to outputs of the interference cancellers, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver means;

summing means for combining output signals of said phase variation cancellers to produce a sum signal;

decision means for comparing said sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the compared signal is higher or lower than the threshold; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to each of said interference cancellers as said correction signal.

19. A receiver as claimed in claim 15 or 16, wherein each of said phase variation cancellers comprises:

delay means for introducing a delay corresponding to one symbol of said DS/CDMA signal into an output signal of a corresponding one of said interference cancellers; and

multiplier means for multiplying the output signal of said corresponding interference canceller with the signal delayed by said delay means.

20. A receiver as claimed in claim 19, wherein each of said phase variation cancellers further comprises an automatic gain controlled amplifier connected to the output of a corresponding one of said interference cancellers for generating a constant amplitude signal and applying the constant amplitude signal to said delay means and said multiplier means.

21. A receiver as claimed in claim 19, wherein each of said phase variation cancellers further comprises a normalizer connected between said delay means and said multiplier means.

22. A receiver as claimed in claim 15 or 16, wherein each of said phase variation cancellers comprises:

means for deriving a reference carrier from input and output signals of said decision means; and

means for synchronizing the output signal of said interference canceller to said reference carrier.

23. A receiver as claimed in claim 22, wherein said reference carrier deriving means comprises:

phase detector means for detecting a phase difference between the input and output signals of said decision means; and

integrator means for integrating said phase difference for producing said reference carrier.

24. A receiver as claimed in claim 22, wherein said synchronizing means comprises a phase shifter for shifting the output signal of said interference canceller according to said reference carrier.

16. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

a delay line connected to said receiver means, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

a plurality of phase variation cancellers connected respectively to outputs of the interference cancellers, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver means;

maximum ratio combiner means for weighting output signals of said phase variation cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

decision means for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold and supplying the output signal of the decision means to said maximum ratio combiner means as said second feedback signal; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to each of said interference cancellers as said first feedback signal.

25. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

an interference canceller connected to said receiver means for cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

latch means having a plurality of elements;

means for sequentially coupling an output signal of said interference canceller to said element of the latch means;

maximum ratio combiner means for weighting output signals of said elements of the latch means according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

decision means for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold, and supplying the output signal of the decision means to said maximum ratio combiner means as said second feedback signal; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to interference cancellers as said first feedback signal.

28. A receiver as claimed in claim 25, 26 or 27, wherein said interference canceller comprises a linear equalizer for cancelling said components according to the error detected by said error detector means.

29. A receiver as claimed in claim 25, 26 or 27, wherein each of said interference cancellers comprises a decision feedback equalizer for cancelling said components according to the error detected by said error detector means and the output signal of said decision means.

26. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

an interference canceller connected to said receiver means for cancelling components of the signal from said desired source according to a correction signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

latch means having a plurality of latch elements;

means for sequentially coupling an output signal of said interference canceller to said elements of the latch means;

a plurality of phase variation cancellers connected respectively to said elements of the latch means, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver means;

summing means for combining output signals of said phase variation cancellers to produce a sum signal;

decision means for comparing said sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the compared signal is higher or lower than the threshold; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to said interference cancellers as said correction signal.

30. A receiver as claimed in claim 26 or 27, wherein each of said phase variation cancellers comprises:

delay means for introducing a delay corresponding to one symbol of said DS/CDMA signal into an output signal of said interference canceller; and

multiplier means for multiplying the output signal of said interference canceller with the signal delayed by said delay means.

31. A receiver as claimed in claim 30, wherein each of said phase variation cancellers further comprises an automatic gain controlled amplifier connected to the output of said interference canceller for generating a constant amplitude signal and applying the constant amplitude signal to said delay means and said multiplier means.

32. A receiver as claimed in claim 30, wherein each of said phase variation cancellers further comprises a normalizer connected between said delay means and said multiplier means.

33. A receiver as claimed in claim 26 or 27, wherein each of said phase variation cancellers comprises:

means for deriving a reference carrier from input and output signals of said decision means; and

means for synchronizing the output signal of said interference canceller to said reference carrier.

34. A receiver as claimed in claim 33, wherein said reference carrier deriving means comprises:

phase detector means for detecting a phase difference between the input and output signals of said decision means; and

integrator means for integrating said phase difference for producing said reference carrier.

35. A receiver as claimed in claim 33, wherein said synchronizing means comprises a phase shifter for shifting the output signal of said interference canceller according to said reference carrier.

27. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

receiver means for receiving said signal from a desired source;

an interference canceller connected to said receiver means for cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver means as a result of multipath fading effect;

latch means having a plurality of latch elements;

means for sequentially coupling an output signal of said interference canceller to said elements of the latch means;

a plurality of phase variation cancellers connected respectively to said elements of the latch means, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver means;

maximum ratio combiner means for weighting output signals of said phase variation cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

decision means for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold and supplying the output signal of the decision means to said maximum ratio combiner means as said second feedback signal; and

error detector means for detecting an error between the input and output signals of said decision means and applying the detected error to said interference canceller as said first feedback signal.

36. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a plurality of signal sources transmit DS/CDMA signals on a radio frequency carrier, each of the DS/CDMA signals being produced by spreading a symbol with a unique spread code at predetermined chip intervals, comprising:

a receiver device having a spectral bandwidth for receiving said DS/CDMA signals;

an interference canceller for cancelling signals from desired sources introduced to a signal received by the receiver device from a desired source by using a feedback signal;

a phase variation canceller for cancelling a fading-related phase variation that occurs between successive symbols of the signal from the desired source;

a decision circuit for comparing an input signal with a decision threshold and producing an output signal representing one of two discrete values depending on whether the input signal is higher or lower than the threshold, the interference canceller and the phase variation canceller being connected in series between said receiver device and said decision circuit for producing an interference- and phase-variation-cancelled signal, and

a correction signal generator for deriving a correction signal from said interference- and phase-variation cancelled signal and applying the correction signal to said interference canceller as said feedback signal,

wherein the interference canceller is a linear equalizer including;

a tapped-delay line having delay-line tap intervals equal to or smaller than said predetermined chip intervals;

a plurality of multipliers connected to successive taps of the delay line for multiplying tap signals on said successive taps with respective tap weight vectors;

an adder for summing outputs of the multipliers to produce a signal as an output signal of the interference canceller; and

a tap-weight controller for deriving said tap weight vectors respectively from correlations between said tap signals and said feedback signal, whereby the tap weight vectors are orthogonally oriented to the signals from the undesired sources.

37. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

a delay line connected to said receiver device, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a maximum ratio combiner for weighting output signals of-said interference cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

a decision circuit for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold, and supplying the output signal of the decision circuit to said maximum ratio combiner as said second feedback signal; and

an error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to each of said interference cancellers as said first feedback signal.

38. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

a delay line connected to said receiver device, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a correction signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a plurality of phase variation cancellers connected respectively to outputs of the interference cancellers, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver device;

a summing device for combining output signals of said phase variation cancellers to produce a sum signal;

a decision circuit for comparing said sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the compared signal is higher or lower than the threshold; and

error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to each of said interference cancellers as said correction signal.

39. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

a delay line connected to said receiver device, the delay line having a plurality of successive taps;

a plurality of interference cancellers connected respectively to said successive taps, each of the interference cancellers cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a plurality of phase variation cancellers connected respectively to outputs of the interference cancellers, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver device;

a maximum ratio combiner for weighting output signals of said phase variation cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

a decision circuit for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold and supplying the output signal of the decision circuit to said maximum ratio combiner as said second feedback signal; and

an error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to each of said interference cancellers as said first feedback signal.

40. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

an interference canceller connected to said receiver device for cancelling components of the signal from said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a latch having a plurality of elements;

a sequential coupling device for sequentially coupling an output signal of said interference canceller to said elements of the latch;

a maximum ratio combiner for weighting output signals of said elements of the latch according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

a decision circuit for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold, and supplying the output signal of the decision circuit to said maximum ratio combiner as said second feedback signal; and

an error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to said interference canceller as said first feedback signal.

41. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

an interference canceller connected to said receiver device for cancelling components of the signal from said desired source according to a correction signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a latch having a plurality of latch elements;

a sequential coupling device for sequentially coupling an output signal of said interference canceller to said elements of the latch;

a plurality of phase variation cancellers connected respectively to said elements of the latch, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver device;

a summing device for combining output signals of said phase variation cancellers to produce a sum signal;

a decision circuit for comparing said sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the compared signal is higher or lower than the threshold; and

an error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to said interference canceller as said correction signal.

42. A receiver for a direct-sequence code division multiple access (DS/CDMA) communication system wherein a symbol is spread with a predetermined spread code to produce a DS/CDMA signal which is transmitted on a radio frequency carrier, comprising:

a receiver device for receiving said signal from a desired source;

an interference canceller connected to said receiver device for cancelling components of the signal for said desired source according to a first feedback signal, said components being introduced to the signal received by the receiver device as a result of multipath fading effect;

a latch having a plurality of latch elements;

a sequential coupling device for sequentially coupling an output signal of said interference canceller to said elements of the latch;

a plurality of phase variation cancellers connected respectively to said elements of the latch, each of the phase variation cancellers cancelling a phase variation that occurs in an interval between successive symbols of the signal received by said receiver device;

a maximum ratio combiner for weighting output signals of said phase variation cancellers according to a second feedback signal and summing the weighted output signals to produce a weighted sum signal;

a decision circuit for comparing said weighted sum signal with a decision threshold to produce an output signal representing one of two discrete values depending on whether the weighted sum signal is higher or lower than the threshold and supplying the output signal of the decision circuit to said maximum ration combiner as said second feedback signal; and

an error detector for detecting an error between the input and output signals of said decision circuit and applying the detected error to said interference canceller as said first feedback signal.