Trench MOS-gated device with a minimum number of masks

• US 5,648,670 A
• Filed: 06/07/1995
• Issued: 07/15/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/474,711
• Time in Patent Office: 769 Days
• Field of Search: 257/329, 257/330, 257/360, 437/41, 437/203, 437/913
• US Class Current: 257/329
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Claims

1. A power transistor device, comprising:

a network of trenches extending into monocrystalline semiconductor material from a first surface thereof;

a first-conductivity-type source diffusion in said semiconductor material at some locations of said first surface thereof adjacent to said trenches, and a second-conductivity-type channel diffusion in said semiconductor material below said source diffusion; and

an insulated conductive gate mesh inlaid into said network of trenches, and capacitively coupled to control conduction through said channel diffusions along sidewalls of said trenches;

said first surface of said semiconductor material being depressed at locations away from said trenches.

2. The integrated circuit of claim 1, wherein said semiconductor material consists of silicon.

3. The integrated circuit of claim 1, wherein said first conductivity type is N-type.

4. The device of claim 1, further comprising an additional second-conductivity-type diffusion which extends into said semiconductor material below the level of said channel diffusion, at said depressed locations.