Endcap chip with conductive, monolithic L-connect for multichip stack

• US 5,648,684 A
• Filed: 07/26/1995
• Issued: 07/15/1997
• Est. Priority Date: 07/26/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude Louis, Howell, Wayne John, Kalter, Howard Leo
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/506,939
• Time in Patent Office: 720 Days
• Field of Search: 257/685, 257/686, 257/723, 257/777
• US Class Current: 257/685
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.

Claims

1. A carrierless endcap chip a multichip stack, said stack including multiple integrated circuit chips laminated together such that at least one principal surface of each integrated circuit chip contacts a principal surface of an adjacent integrated circuit chip in the multichip stack, said endcap chip comprising:

a substrate of semiconductor material having an upper surface, a lower surface and an edge surface, said edge surface extending in a plane substantially orthogonal to a plane containing said upper surface, and said lower surface contacting a principal surface of an adjacent integrated circuit chip of said stack; and

a conductive, monolithic L-connect integral with the substrate and having a first leg extending at least partially over said upper surface of said substrate and a second leg extending at least partially over said edge surface of said substrate, said second leg having a substantially planar outer surface, wherein when said endcap chip is employed as an end chip within said multichip stack, said conductive, monolithic L-connect electrically interconnects metal on an end face of said multichip stack and metal on a side face of said multichip stack, said side face being parallel to said edge surface of said substrate, and said end face being defined by the upper surface of said substrate.

2. The endcap chip of claim 1, wherein said semiconductor material comprises silicon.

3. The endcap chip of claim 1, wherein said metal on said side face of said multichip stack comprises a first type of metal, and wherein said conductive, monolithic L-connect also comprises said first type of metal.

4. The endcap chip of claim 1, wherein said substrate has a thickness measured from said lower surface to said upper surface of less than 100 μ

m.

5. The endcap chip of claim 1, wherein said substrate has a rectangular configuration with four edges, said edge surface comprising a first edge of said four edges, and wherein said endcap chip further comprises at least one additional conductive, monolithic L-connect having a first leg extending at least partially over said upper surface of said substrate and a second leg extending at least partially over a second edge of said substrate, said second edge being different from said first edge.

6. The endcap chip of claim 5, wherein said first leg of said conductive, monolithic L-connect and said first leg of said at least one additional conductive, monolithic L-connect comprise different metal levels above said upper surface of said substrate.

7. The endcap chip of claim 1, wherein said endcap chip further comprises an active integrated circuit region supported by said substrate.

8. A multichip stack comprising:

a plurality of integrated circuit chips laminated together such that at least one principal surface of each integrated circuit chip contacts a principal surface of an adjacent integrated circuit chip;

an endcap chip comprised of semiconductor material and having a first principal surface, a second principal surface and an edge surface, said edge surface residing in a plane substantially orthogonal to said first principal surface and said second principal surface, said second principal surface of said endcap chip contacting a principal surface of an end integrated circuit chip of said plurality of integrated circuit chips, said endcap chip further including a conductive, monolithic L-connect integral with said endcap chip and having a first leg extending at least partially over said first principal surface and a second leg extending at least partially over said edge surface, said second leg having a substantially planar outer surface;

a first metallization disposed on a side face formed by said plurality of integrated circuit chips and said endcap chip, and a second metallization disposed over an end face defined by said first principal surface of said endcap chip; and

wherein said conductive, monolithic L-connect of said endcap chip electrically connects said first metallization on said side face and said second metallization on said end face of said multichip stack.

9. The multichip stack of claim 8, wherein at least some integrated circuit chips of said plurality of said integrated circuit chips have silicon substrates and said endcap chip has a silicon substrate.

10. The multichip stack of claim 9, wherein said endcap chip includes an active integrated circuit region.

11. The multichip stack of claim 8, wherein said first metallization disposed on said side face comprises a first type of metal and wherein said conductive, monolithic L-connect of said endcap chip also comprises said first type of metal.

12. The multichip stack of claim 8, wherein each chip of said plurality of integrated circuit chips and said endcap chip has a rectangular configuration with four edges, said edge surface of said endcap chip comprising a first edge of said four edges of said endcap chip, and wherein said endcap chip further comprises at least one additional conductive, integral monolithic L-connect having a first leg extending at least partially over said upper surface and a second leg with a substantially planar outer surface extending at least partially over a second edge, said second edge being different from said first edge, and wherein said multichip stack further comprises a third metallization disposed on a second side face such that said at least one additional conductive, monolithic L-connect electrically connects said third metallization on said second side face and said second metallization on said end face of said multichip stack.

13. The multichip stack of claim 12, wherein said first leg of said conductive, monolithic L-connect and said first leg of said at least one additional conductive, monolithic L-connect comprise different metal levels disposed above said first principal surface of said endcap chip.

14. The multichip stack of claim 8, wherein said first metallization directly physically attaches to said second leg of said conductive, monolithic L-connect.

15. The multichip stack of claim 14, wherein at least some integrated circuit chips of said plurality of integrated circuit chips include transfer wirings to said side face, and wherein said first metallization electrically couples to said transfer wirings via standard T-connects.

16. The multichip stack of claim 14, wherein at least some integrated circuit chips of said plurality of integrated circuit chips include transfer wirings to said side face, and wherein said first metallization directly physically attaches to said transfer wirings.

17. The multichip stack of claim 8, wherein each chip of said plurality of integrated circuit chips and said endcap chip is rectangular shaped and has a width defined within lithographic tolerances.

18. The multichip stack of claim 8, wherein each chip of said plurality of integrated circuit chips and said endcap chip has a thickness of less than 100 μ

m.

19. A carrierless chip of a multichip stack comprising:

a substrate of semiconductor material having an upper surface, a lower surface and an edge surface, said edge surface extending in a plane substantially orthogonal to a plane containing said upper surface, and said lower surface contacting a principal surface of an adjacent integrated circuit chip of said stack; and

a conductive, monolithic L-connect integral with the substrate and having a first leg extending at least partially over said upper surface of said substrate and a second leg extending at least partially over said edge surface of said substrate, said second leg having a substantially planar outer surface, wherein when said chip is employed within said multichip stack, said conductive, monolithic L-connect electrically connects to metal on a side face of said multichip stack, said side face being parallel to said edge surface of said substrate.

20. The chip of claim 19 wherein said metal on the side face of said multichip stack comprises a photolithographically defined thin film metal layer.