Reliable ATM microwave link and network

• US 5,648,969 A
• Filed: 02/13/1995
• Issued: 07/15/1997
• Est. Priority Date: 02/13/1995
• Status: Expired due to Term

• Current Assignee: Quarterhill Inc. (f/k/a Wi-LAN Inc.)
• Original Assignee: Netro Corporation (Bonterra Energy Corp.)
• Inventors: BenEfraim, Gideon, Pasternak, Eliezer
• Primary Examiner(s): Chin, Wellington
• Application Number:
  US08/388,110
• Time in Patent Office: 883 Days
• Field of Search: 370/60, 370/60.1, 370/94.1, 370/94.2, 370/97, 370/95.1, 370/95.3
• US Class Current: 370/349
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control
• CPC Class Codes: H04L 2012/5607 Radio
• CPC Class Codes: H04L 2012/561 Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5619 Network Node Interface, e.g. tandem connections, transit switching
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5671 Support of voice
• CPC Class Codes: H04L 2012/5673 Coding or scrambling
• CPC Class Codes: H04L 49/107 using shared medium
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A digital radio link suitable for transmitting digital voice or data signals includes an input circuit for ATM or equivalent cells, a processing circuit to encapsulate the input cells received by the input circuit with at least error check bits so that detected error can identify a specific cell or group of cells, a digital transmission circuit for transmitting the encapsulated cells via a wireless link, a reception circuit for receiving encapsulated cells from an opposite side of the digital radio link, a cell decapsulation and error detection circuit connected to said reception circuit and a cell output circuit for connecting said decapsulation circuit to a digital access unit. The system includes structure for allocating more than one type of service, such as low delay service for voice transmission and extensive forward error correction service for data transmission.

Claims

1. A digital radio link including:

an input circuit for ATM or equivalent cells from a digital access unit;

a cell processing circuit, connected to said input circuit, that encapsulates said input cells with at least error check bits so that a detected error can identify a specific cell or group of cells;

a digital transmission circuit connected to said processing circuit for transmitting said encapsulated cells via a wireless link;

a reception circuit for receiving encapsulated cells;

a cell decapsulation and error detection circuit connected to said reception circuit; and

a cell output circuit for connecting said decapsulation circuit to a digital access unit.

2. The digital radio link of claim 1 wherein said cell processing circuit further includes:

means for allocating more than one type of service, such as low delay for voice and extensive forward error correction for data.

3. A metropolitan area network comprising:

at least two digital radio links of claim 1; and

drop/insert means for separating local passing cells from flow through cells.

4. A digital radio link as in claim 1 wherein said input circuit, said cell processing circuit, said transceiver circuit, said reception circuit and said output circuit are at the same terminal.

5. A digital radio link as in claim 1 wherein said input circuit, said cell processing circuit and said digital transmission circuit are at one terminal and said reception circuit, said cell decapsulation and error detection circuit and said cell output circuit are at a second terminal.

6. Structure as in claim 1 wherein said cell processing circuit comprises a trunk unit, said trunk unit including:

means for identifying cell boundaries,

means for encapsulating cells; and

means for adding forward error correction to the cells.

7. Structure as in claim 6 including means for outputting from said cell processing circuit a bit stream to the digital transmission circuit.

8. Structure as in claim 7 wherein said means for transmitting the bit stream to the digital transmission circuit comprises a selected transmission medium.

9. Structure as in claim 8 wherein said selected transmission medium is one of a twisted pair cable, a coaxial cable and a fiber optics link.

10. Structure as in claim 6 including an interconnect unit for interconnecting a plurality of input circuits and trunk units to enable such input circuits and trunk units to exchange cells among themselves.

11. Structure as in claim 10 including a network management system for instructing each input circuit and trunk unit connected to the interconnect unit as to the destination of each cell being routed through the interconnect unit.

12. Structure as in claim 11 wherein said instruction to each unit connected to the interconnect unit is based upon a connection identification number.

13. Structure of claim 12 wherein said identification number includes a signal denoted as VPI/VCI associated with each cell (in ATM terminology).

14. Structure as in claim 13 including means for identifying the VPI/VCI of each cell and for dropping or picking up only those cells with a VPI/VCI on a list stored in memory in the trunk unit.

15. Structure as in claim 14 including means for replacing an idle cell with an information-bearing cell, said information-bearing cell being maintained in a queue from which information cells are to be provided for transmission in place of an idle cell whenever an idle cell is encountered.

16. Structure as in claim 6 including a cell switching matrix for allowing one input circuit to exchange cells with another input circuit.

17. Structure as in claim 16 including means for interconnecting a plurality of input circuits thereby to allow redundancy.

18. Structure as in claim 17 including a fast flowthrough bus for allowing data to bypass the interface to thus speed the system in appropriate circumstances.

19. Structure as in claim 1 wherein said cell decapsulation and error detection circuit includes:

means for identifying cells in a received bit stream;

means for detecting errors in cells; and

means for dropping cells that are not recoverable.

20. Structure as in claim 19 including means for delivering good cells to the cell output circuit unit.

21. Structure as in claim 20 including means for reporting cell losses to a control system.

22. Structure as in claim 21 wherein said control system includes a microprocessor circuit.

23. Structure as in claim 1 wherein said digital access unit is capable of interfacing with a variety of local interfaces.

24. A cell transmission/reception process including:

inputting cells;

encapsulating said cells by forward error correction bits;

transmitting these cells;

receiving cells from an opposite side of a link;

decapsulating these cells;

dropping or marking "invalid" cells with errors; and

outputting the non-dropped cells.

25. A digital radio terminal in a wireless link including:

an input circuit for inputting ATM cells or equivalent cells from a digital access unit;

a transmit processing circuit connected to said input circuit that encapsulates said input cells into data blocks containing also at least error check bits so that errors on the link could be detected;

a digital transmission circuit connected directly or via cables to a wireless transceiver;

a reception circuit connected to said cables for receiving encapsulated cells from a digital radio terminal at the opposite side of the radio link;

a cell decapsulation and error detection circuit connected to said reception circuit;

a cell processing circuit connected to said cell reception circuit including means for recognizing cell boundaries and rejecting or marking for rejection whole cells upon received indication of errors; and

a cell output circuit for connecting said cell processing circuit to a digital access unit.

26. The digital radio terminal of claim 25 wherein said cell processing circuit further includes means for encapsulating one or more cells on cell boundaries.

27. The digital radio terminal of claim 26 wherein said cell processing circuit further includes:

means for retransmitting cells upon reception of an error indication from a terminal at the opposite side of the link.

28. The digital radio terminal of claim 27 wherein said cell processing circuit further includes:

means for allocating more than one type of service, such as low delay for voice and extensive forward error correction for data.

29. The structure of claim 28 further including two stages of error correction, wherein an error correction phase 1 performs the same level of error correction on all cells, and phase 2 performs selective error correction based on the class of service of each cell.

30. The structure of claim 29 wherein said means for allocation of service include means for automatically constructing a VPI/VCI lookup table.

31. The structure of claim 30 in which said means for automatically constructing includes means for identification of cell type by observing the ATM adaptation layer (AAL) information.

32. A metropolitan area wireless network node comprising at least two digital radio terminals of claim 25 and further including an interconnect unit with cell switching capability, connected to said access units and said transmit and receive circuit so that said interconnect unit can switch ATM or similar cells among all said units and circuits.

33. A cell transmission/reception process including:

inputting cells;

encapsulating said cells by forward error correction bits;

transmitting these encapsulated cells on a link;

receiving cells from an opposite side of a link;

decapsulating these cells;

delineating cell boundaries;

dropping or marking "invalid" cells with errors; and

outputting the non-dropped cells.

34. A digital radio system including:

a plurality of input circuits for ATM or equivalent cells from a digital access unit;

a plurality of cell processing circuits, each cell processing circuit being connected uniquely to a corresponding input circuit, each cell processing circuit being capable of encapsulating input cells with at least error check bits so that a detected error can be pinpointed to a specific cell or group of cells;

a plurality of digital transmission circuits, each digital transmission circuit being connected to a corresponding one of said processing circuits for transmitting encapsulated cells via a wireless link;

a plurality of reception circuits for receiving encapsulated cells from an opposite side of a digital radio link;

a plurality of cell decapsulation and error detection circuits, each cell decapsulation and error detection circuit being connected uniquely to a corresponding one of said plurality of reception circuits; and

a plurality of cell output circuits, each cell output circuit connecting a corresponding one of said decapsulation and error detection circuits to a corresponding digital access unit.