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Data processor with a multi-level protection mechanism, multi-level protection circuit, and method therefor

  • US 5,649,159 A
  • Filed: 05/22/1995
  • Issued: 07/15/1997
  • Est. Priority Date: 08/31/1994
  • Status: Expired due to Term
First Claim
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1. A data processor (30) with a multi-level protection mechanism, comprising:

  • a central processing unit (CPU) (31) for generating an address and at least one corresponding control signal sequentially for each of a plurality of memory accesses, in response to a program; and

    a multi-level protection circuit (50) coupled to said CPU (31), comprising;

    a first decoder (51) having a first input for receiving said address, a second input for receiving said at least one corresponding control signal, a first output for providing a first address match signal if said address is within a first programmable region (41), and a second output for providing a first attribute match signal if said at least one corresponding control signal matches a first programmable protection attribute;

    a second decoder (54) having a first input for receiving said address, a second input for receiving said at least one corresponding control signal, a first output for providing a second address match signal if said address is within a second programmable region (42), and a second output for providing a second attribute match signal if said at least one corresponding control signal matches a second programmable protection attribute; and

    a priority enforcing circuit (58) having inputs for receiving said first and second outputs of each of said first (51) and second (54) decoders, and an output for providing an enable signal for enabling a generation of at least one external control signal for accessing an external device (22, 23, 24,

         25),said priority enforcing circuit (58) activating said enable signal if only one of said first and second address match signals are active and a corresponding one of said first and second attribute match signals are active,said priority enforcing circuit (58) keeping said enable signal inactive if both said first and second address match signals are active and said second attribute match signal is inactive,whereby said second programmable region (42) may overlap said first programmable region (41).

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