Methods for controlling timing in a logic emulation system

• US 5,649,167 A
• Filed: 06/07/1995
• Issued: 07/15/1997
• Est. Priority Date: 01/31/1992
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Li, Jeong-Tyng, Huang, Thomas B., Wang, Ming-Yang, Chen, Nang-Ping, Ko, Robert J.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/472,531
• Time in Patent Office: 769 Days
• Field of Search: 395/500, 375/354, 375/356, 364/488, 364/489, 364/490, 364/491
• US Class Current: 703/23
• CPC Class Codes: A21B 1/245 with a plurality of air nozzles to obtain an impingement effect on the food
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

Claims

1. A method for implementing a netlist description of an integrated circuit in a plurality of reprogrammable logic circuits comprising the steps of:

analyzing the netlist description to find a first storage instance and a second storage instance having a data path structure between them and being clocked by different clock signals;

implementing said first and said second storage instances respectfully in a first and a second of the plurality of reprogrammable logic circuits; and

implementing said data path structure in a third of the plurality of reprogrammable logic circuits in order create a predetermined amount of delay in said data path structure between said first and second storage instance.