Dynamic instruction allocation for a SIMD processor

• US 5,649,179 A
• Filed: 05/19/1995
• Issued: 07/15/1997
• Est. Priority Date: 05/19/1995
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gehman, John Bartholomew Jr., Steenstra, Mark Evan, Acosta, Ascencion Chapapro Jr.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/444,637
• Time in Patent Office: 788 Days
• Field of Search: 345/800, 395/379, 395/385, 395/595, 395/598, 395/388
• US Class Current: 712/248
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A method and apparatus to dynamically allocate instructions to programmable processing element decoders (78, 79, 80) in a SIMD processor (100) includes a source code instruction (71) for the processor is parsed (1) into components (75, 76, 77) that apply to specific processing elements (60, 61, 62). The components (75, 76, 77) are used to determine control signals (90, 91, 92) that must be generated from the processing element instruction decoders (50, 51, 52) in order to execute the given instruction. If a processing element instruction decoder (50, 51, 52) is not capable of producing the necessary control signals (90, 91, 92), the decoder (50, 51, 52) must be reconfigured to do so. Then the processing element instruction (75, 76, 77) that will generate the specified control logic can be determined and returned to the assembler or compiler so that the assembly or compilation of the program can be completed.

Claims

1. A method of dynamically allocating a processing element instruction to a processing element in a single instruction multiple data (SIMD) processor, comprising the steps of:

parsing a source code instruction for the SIMD processor into components applicable to the processing element instruction;

assembling the components into a control specification for the processing element;

updating an instruction decoder configuration according to the control specification if necessary for the processing element; and

determining the processing element instruction for the processing element.

2. A method as claimed in claim 1, wherein the step of assembling comprises the step of providing an array representing the control specification, such that elements of the array represent digital control signals for the processing element.

3. A method as claimed in claim 2, wherein the step of assembling further comprises the step of initializing all of the elements of the array to a symbol representing that values of the elements are undefined.

4. A method as claimed in claim 3, wherein the step of assembling further comprises the step of setting values of the elements to a logical one, logical zero, or logical X, where the logical X can be either the logical one or the logical zero, according to the components parsed from the source code instruction, such that the source code instruction will be executed.

5. A method as claimed in claim 1, wherein the step of assembling further comprises the step of setting default values for elements that remain undefined.

6. A method as claimed in claim 1, wherein the step of updating comprises the step of determining if the instruction decoder configuration must be modified in order to generate a control word according to the control specification.

7. A method as claimed in claim 6, wherein the step of updating further comprises the step of determining if the instruction decoder configuration must be modified in order to generate the control word according to a user defined superset of the control specification.

8. A method as claimed in claim 7, wherein the step of updating further comprises the step of updating the instruction decoder configuration if necessary.

9. A method as claimed in claim 8, wherein the step of determining if the instruction decoder configuration must be modified in order to generate the control word according to the control specification comprises the step of determining if a decoder store load table representing a plurality of unique control words that are stored in a decoder store contains the control word.

10. A method as claimed in claim 8, wherein the step of determining if the instruction decoder configuration must be modified in order to generate the control word according to the control specification comprises the step of determining if a programmable logic decoder is capable of generating the control word when configured using a configuration file that controls the operation of a programmable logic decoder.

11. A single-instruction multiple-datapath (SIMD) processor comprising:

processing elements;

processing element instruction decoders; and

processing element instruction decoder reconfigurers which map instructions targeted at the processing element instruction decoders.

12. A processor as claimed in claim 11, wherein the processing element instruction decoders comprise a decoder store load table representing a plurality of unique stored control words.

13. A processor as claimed in claim 11, wherein the processing element instruction decoders comprise a configuration file that controls operation of a programmable logic decoder.

14. A method of dynamically allocating instructions to a programmable processing element decoder in a single instruction multiple data (SIMD) processor, the method comprising the steps of:

parsing a source code instruction for the SIMD processor into components applicable to the instructions;

assembling the components into a control specification for the programmable processing element decoder;

updating an instruction decoder configuration according to the control specification; and

determining the instructions.

15. A method as claimed in claim 14, wherein the step of assembling comprises the steps of:

providing an array representing the control specification, such that elements of the array represent digital control signals;

initializing all of the elements of the array to a symbol representing that values of the elements are undefined;

setting values of the elements to a logical one, logical zero, or logical X, where the logical X can be either the logical one or logical zero, according to the components parsed from the source code instruction, such that the source code instruction will be executed; and

setting default values for elements that remain undefined.

16. A method as claimed in claim 14, wherein the step of updating comprises the steps of:

determining if the instruction decoder configuration must be modified in order to generate a control word according to the control specification;

determining if the instruction decoder configuration must be modified in order to generate the control word according to a user defined superset of the control specification; and

updating the instruction decoder configuration if necessary.

17. A method as claimed in claim 16, wherein the step of determining if the instruction decoder configuration must be modified in order to generate the control word according to the control specification comprises the step of determining if a decoder store load table representing a plurality of unique control words that are stored in a decoder store contains the control word.

18. A method as claimed in claim 16, wherein the step of determining if the instruction decoder configuration must be modified in order to generate a control word according to the control specification comprises the step of determining if a programmable logic decoder is capable of generating the control word when configured using a configuration file that controls the operation of a programmable logic decoder.