Active matrix display and electrooptical device

• US 5,650,636 A
• Filed: 06/01/1995
• Issued: 07/22/1997
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Konuma, Toshimitsu, Hamatani, Toshiji, Takemura, Yasuhiko, Koyama, Jun, Yamazaki, Shunpei, Zhang, Hongyong, Kawasaki, Yuji
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/456,404
• Time in Patent Office: 782 Days
• Field of Search: 257/59, 257/72, 257/532, 257/536, 359/54, 359/59, 359/87, 340/719
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A structure for reducing the OFF current of an active matrix display. In the active matrix display, plural TFTs are connected in series with each one pixel electrode. Of these TFTs connected in series, at least one TFT excluding the TFTs located at opposite ends is maintained in conduction. Alternatively, at least one capacitor is connected between the junction of the drain and source of each TFT connected in series and an AC grounded point. Thus, the amount of electric charge released from auxiliary capacitors during cutoff of the TFTs is reduced.

Claims

1. An active matrix display comprising:

pixel electrodes arranged in rows and columns;

semiconductor film islands, each one of said islands being provided for each one of said pixel electrodes, said islands having N- or P-type regions; and

at least three gate electrodes provided on each one of said semiconductor film islands and coated with an anodic oxide film to provide at least three thin film transistors on said each one of said semiconductor film islands, said three thin film transistors having three gate electrodes respectively, said three thin film transistors being connected in series with each other with gates of two of said three thin film transistors being connected with a gate signal line, and a gate of the other of said three thin film transistors being connected with a capacitor line,

wherein one of source and drain of the other of said three thin film transistors is connected with one of source and drain of one of said two of said three thin film transistors, and the other of the source and drain of the other of said three thin film transistors is connected with one of source and drain of the other of said two of said three thin film transistors, and the other of the source and drain of said one of said two of said three thin film transistors is connected with an image signal line, and the other of the source and drain of the other of said two of said three thin film transistors is connected with the corresponding one of said pixel electrodes, and

wherein said gate connected with said capacitor line is applied with a signal which activates said gate connected with said capacitor line at least for a major portion of a time during which a select signal is not applied to the gate signal line.

2. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

a first line arranged in a substantially horizontal direction;

at least two of first thin-film transistors provided in said pixel region, said at least two of first transistors having at least two gate electrodes respectively, said two gate electrodes being connected to said first line;

a second line arranged in parallel to said first line; and

at least one of second thin-film transistor provided in said pixel region, a gate electrode of said second transistor being connected to said second line,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first thin-film transistors, and the other of the source and drain of said one of said first thin-film transistors is connected with said pixel electrode, and the other of the source and drain of the other of said first thin-film transistors is connected with an image signal line.

3. The display of claim 2 wherein the other of said first transistors is connected to an image signal line, said image signal line is arranged in a substantially vertical direction.

4. The display of claim 2 wherein said second transistor is connected between said two first transistors.

5. The display of claim 2 wherein said first transistor has an offset gate structure that a gate electrode thereof aparts from source and drain regions.

6. The display of claim 2 wherein a surface of said first transistor is covered with an anodic oxide film.

7. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

a first line arranged in a substantially horizontal direction;

at least two of first thin-film transistors provided in said pixel region, said at least two of first transistors having at least two gate electrodes respectively,, said two gate electrodes being connected to said first line;

a second line arranged in parallel to said first line; and

at least one of second thin-film transistor provided in said pixel region, a gate electrode of said second transistor being connected to said second line,

wherein said second transistor has an offset gate structure that said gate electrode of said second transistor aparts from source and drain regions of said second transistor,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first think-film transistors, and the other of the source and drain of said one of said first thin-film transistors is connected with said pixel electrode, and the other of the source and drain of the other of said first thin-film transistors is connected with an image signal line.

8. The display of claim 7 wherein one of said first transistors is connected to an image signal line arranged in a substantially vertical direction and the other of said first transistors is connected said pixel electrode.

9. The display of claim 7 wherein a surface of said second transistor is covered with an anodic oxide film.

10. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

a first line arranged in a substantially horizontal direction;

at least two of first thin-film transistors provided in said pixel region, said at least two of first transistor having at least two gate electrodes respectively, said two gate electrodes being connected to said first line;

a second line arranged in parallel to said first line; and

at least one of second thin-film transistor provided in said pixel region, a gate electrode of said second transistor being connected to said second line,

wherein ions are lightly doped into at least one portion of a channel region of said second transistor,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first thin-film transistors, and the other of the source and drain of said one of said first thin-film transistors is connected with said pixel electrode, and the other of the source and drain of the other of said first thin-film transistors is connected with an image signal line.

11. The display of claim 10 wherein one of said first transistors is connected to an image signal line arranged in a substantially vertical direction and the other of said first transistors is connected said pixel electrode.

12. The display of claim 10 wherein said lightly doped region constitutes of a resistor, said resistor being connected between said two first transistors.

13. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

gate signal lines arranged in columns;

image signal lines arranged in rows;

capacitor lines arranged in parallel to said gate signal lines;

at least two of first thin-film transistors provided in said pixel region and having at least two gate electrodes respectively, said two gate electrodes being connected to said gate signal line; and

a capacitor connected between said two first transistors, said capacitor being constituted of a second thin-film transistor having a gate electrode connected with said capacitor line,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first thin-film transistors, and the other of the source and drain of said one of said first thin-film transistors is connected with said pixel electrode, and the other of the source and drain of the other of said first thin-film transistors is connected with said image signal line.

14. The display of claim 13 wherein said second transistor is maintained in conduction.

15. The display of claim 13 wherein said second transistor is connected to a capacitor line provided in parallel to said gate signal line, said second transistor being maintained in conduction during at least non-selection period of said gate signal and

said capacitor line is provided in order to maintain a gate electrode of said second transistor at a predetermined potential.

16. The display of claim 13 wherein said capacitor is provided in order to delay a voltage drop between a source and a drain of said first transistor connected to said pixel electrode during said non-selection period.

17. The display of claim 13 wherein said capacitor is a MOS capacitor including a gate insulating film and a gate electrode which are provided on a semiconductor film.

18. The display of claim 13 wherein said second transistor includes an anodic oxide film formed on a gate electrode,

said pixel electrode is extended and

said capacitor is constituted of said gate electrode, said anodic oxide film and said extended pixel electrode.

19. The display of claim 13 wherein at least one resistor is connected between said two first transistors.

20. The display of claim 13 wherein said resistor is constituted by lightly doping ions into a channel region of said first transistor.

21. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

gate signal lines arranged in columns;

image signal lines arranged in rows;

capacitor lines arranged in parallel to said gate signal lines;

at least two of first thin-film transistors provided in said pixel region and having at least two gate electrodes respectively, said two gate electrodes being connected to said gate signal line;

a first capacitor connected between said two first transistors;

said capacitor being constituted of a second thin-film transistor having a gate electrode connected with said capacitor line; and

a second capacitor connected to said pixel electrode,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first thin-film transistors, and the other of the source and drain of said one of said first thin-film transistors is connected with said pixel electrode, and the other of the source and drain of the other of said first thin-film transistors is connected with said image signal line.

22. The display of claim 21 wherein said first capacitor is constituted of a second thin-film transistor.

23. The display of claim 21 wherein said one of said first transistors is connected to said image signal line and the other is connected to said pixel electrode.

24. An active matrix display comprising:

pixel electrodes arranged in a matrix form;

gate signal lines arranged in columns;

image signal lines arranged in rows;

capacitor lines arranged in parallel to said gate signal lines;

a plurality of first thin-film transistors formed between said capacitor line and gate line, each of said first thin-film transistors having a gate electrode connected with said gate signal line;

a capacitor formed with said capacitor line, said capacitor being constituted of a second thin-film transistor having a gate electrode connected with said capacitor line,

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors connected with said image signal line, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of another of said first thin-film transistors connected with said pixel electrode.

25. The display of claim 24 wherein said capacitor line is provided in order to maintain a gate electrode of said second transistor at a predetermined potential.

26. An active matrix display comprising:

at least one pixel region arranged in a matrix form, said pixel region including a pixel electrode;

a first line arranged in a substantially horizontal direction;

at least two of first thin-film transistors each including a source region, a drain region and a channel region and provided in said pixel region, said at least two of first transistors having at least two gate electrodes respectively, said two gate electrodes being connected to said first line;

a second line arranged in parallel to said first line; and

an image signal line arranged in a substantially vertical direction;

at least one of second thin-film transistor provided in said pixel region, a gate electrode of said second transistor being connected to said second line;

wherein one of source and drain of said second thin-film transistor is connected with one of source and drain of one of said first thin-film transistors, and the other of the source and drain of said second thin-film transistor is connected with one of source and drain of the other of said first thin-film transistors, and the other of the source and drain of the other of said first thin-film transistors is connected with an image signal line, and

wherein said channel region is extended in parallel to said image signal line and positioned below said image signal line.

27. The display of claim 26 wherein one of said source and drain regions is connected to said pixel electrode and the other of said source and drain regions is connected to said image signal line.

28. The display of claim 26 wherein said gate signal line serves as a light-shielding film for said channel region.