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Drive circuit with rise and fall time equalization

  • US 5,650,801 A
  • Filed: 06/07/1995
  • Issued: 07/22/1997
  • Est. Priority Date: 06/07/1994
  • Status: Expired due to Term
First Claim
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1. A CMOS driving circuit for a capacitive load, which produces a three-level, symmetrical AC scanning voltage waveform having opposed large amplitude HIGH and LOW voltages for column-select and a GROUND voltage for column-nonselect, comprising:

  • HIGH, LOW, and GROUND supply terminals respectively for receiving opposed large amplitude HIGH and LOW voltages and a GROUND voltage;

    separate inputs for HIGH-SELECT, LOW-SELECT, and GROUND-SELECT signals, each of which can be either at the HIGH or LOW voltage, and a common output;

    a p-channel MOSFET normally OFF but responsive to the HIGH-SELECT signal being HIGH for coupling the HIGH terminal to the common output;

    a discharging circuit having a pair of n-channel MOSFETs for coupling the GROUND terminal to the common output when the GROUND-SELECT signal is HIGH, and an AND gate for disabling one of the pair of n-channel MOSFETs from such coupling when the common output is at a voltage lower than GROUND; and

    an individual n-channel MOSFET, normally OFF but responsive to the LOW-SELECT signal being HIGH for coupling the LOW terminal to the common output;

    whereby the rise and fall times of the scanning voltage waveform are kept the same without sacrificing a high breakdown voltage.

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