Programmable data acquisition system with a microprocessor for correcting magnitude and phase of quantized signals while providing a substantially linear phase response

• US 5,650,951 A
• Filed: 06/02/1995
• Issued: 07/22/1997
• Est. Priority Date: 06/02/1995
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Staver, Daniel Arthur
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/459,852
• Time in Patent Office: 781 Days
• Field of Search: 364/724.1, 364/724.13, 364/825
• US Class Current: 708/313
• CPC Class Codes: H03M 3/378 Testing
• CPC Class Codes: H03M 3/466 Multiplexed conversion systems

Abstract

A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system. The data acquisition system is coupled to an external microprocessor having a magnitude and a phase corrector through a microprocessor interface that transfers a microprocessor-derived control word from the microprocessor to the control unit. The microprocessor interface further transfers the stream of quantized electrical signals supplied by the converter system to the microprocessor. The phase corrector provides a predetermined phase angle correction over a predetermined passband to the quantized signals transferred to the microprocessor from the converter system while the magnitude corrector provides a predetermined magnitude correction over the predetermined passband.

Claims

1. A programmable data acquisition system comprising:

a plurality of input signal channels for receiving a respective input signal during a normal mode of operation;

circuit means for selecting respective ones of said plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in said data acquisition system;

an analog-to-digital converter system for supplying a stream of quantized electrical signals at a predetermined rate, said converter system being responsive to any signals carried in said plurality of signal channels as selected by said circuit means;

a control unit for supplying respective control signals to the circuit means and to the converter system; and

a microprocessor interface coupling said control unit to an external microprocessor having a magnitude corrector and a phase corrector, said microprocessor interface providing a microprocessor-derived control word from said microprocessor to said control unit, said microprocessor interface further transferring the stream of quantized electrical signals supplied by the converter system to said microprocessor so that said phase corrector provides a predetermined phase angle correction over a predetermined passband to the quantized signals transferred to said microprocessor from said converter system while said magnitude corrector provides a predetermined magnitude correction over said predetermined passband, said magnitude and phase correctors each having a substantially linear phase response over said predetermined passband.

2. The data acquisition system of claim 1 wherein said converter system comprises a plurality of sigma-delta modulators and a corresponding plurality of decimation filters having a selectable decimation ratio, each respective one of said decimation filters being coupled to receive an output signal from a respective one of said sigma-delta modulators and providing a respective filtered output signal.

3. The data acquisition system of claim 2 wherein said magnitude corrector comprises an infinite impulse response (IIR) digital filter having a z domain response H(z) defined by:

##EQU2## wherein α

is a number such that |α

|<

1.

4. The data acquisition system of claim 3 wherein said IIR digital filter for said magnitude corrector comprises:

a digital subtractor for receiving each filtered output signal from said decimation filters as a minuend input signal and for receiving a subtrahend feedback signal, said digital subtractor adapted to produce a difference output signal;

a delay unit coupled to receive said difference output signal so as to produce a delayed difference signal; and

a digital multiplier coupled to receive said delayed difference signal and adapted to multiply said delayed difference signal by a multiplying factor substantially corresponding to said α

number, the output signal of said multiplier constituting said subtrahend feedback signal and the output signal of said subtractor constituting the output signal of said IIR filter.

5. The data acquisition system of claim 3 wherein said phase corrector comprises an infinite impulse response (IIR) digital filter having a z domain response defined by:

##EQU3## wherein α

is a number such that |α

|<

1.

6. The data acquisition system of claim 5 further comprising at least one feedback generating circuit for generating a measurement signal supplied to a respective one of said signal channels.

7. The data acquisition system of claim 6 wherein said feedback generating circuit comprises:

an operational amplifier; and

a switching assembly for generating a compensating AC signal from a DC offset voltage across the input ports of said operational amplifier, said switching assembly being switched at a selectable rate in response to a switching signal.

8. The data acquisition system of claim 7 wherein said operational amplifier includes first and second differential input ports and first and second differential output ports.

9. The data acquisition system of claim 7 wherein said control unit includes a programmable clock module for generating the switching signal applied to said switching assembly.

10. The data acquisition system of claim 9 wherein said microprocessor interface further comprises a protocol interface selector.

11. The data acquisition system of claim 10 further comprising a power-fail detector for generating an output signal indicative of a predetermined power-fail condition in said data acquisition system.

12. The data acquisition system of claim 11 wherein said microprocessor interface transfers respective digital measurements of the switching signal generated by said programmable clock module and the output signal from said power-fail detector.

13. The data acquisition system of claim 2 wherein said phase corrector comprises an infinite impulse response (IIR) digital filter having a z domain response defined by:

##EQU4## wherein α

is a number such that |α

|<

1.

14. The data acquisition system of claim 13 wherein said IIR digital filter for said phase corrector comprises:

a first digital summer having first and second inputs, said first digital summer for receiving at the first input thereof each filtered output signal from said decimation filters and for receiving at the second input thereof a feedback signal, said first digital summer adapted to produce a respective combined output signal;

a digital multiplier coupled to said first digital multiplier to receive the combined output signal produced therein and adapted to multiply said received combined output signal by a multiplying factor substantially corresponding to said α

number;

a digital subtractor for receiving the filtered signal from said decimation filter as a minuend input signal and for receiving the output signal from said multiplier as a subtrahend input signal, said digital subtractor adapted to produce a difference output signal;

a delay unit coupled to said digital subtractor to receive the difference output signal produced therein and adapted to produce a delayed difference signal constituting the feedback signal received by said first digital summer; and

a second digital summer having first and second inputs, said second digital summer for receiving at the first input thereof the delayed difference signal and for receiving at the second input thereof the output signal from said multiplier, said second digital summer adapted to produce a combined output signal constituting the output signal of said IIR filter.