Internetworking device with enhanced packet header translation and memory

• US 5,651,002 A
• Filed: 07/12/1995
• Issued: 07/22/1997
• Est. Priority Date: 07/12/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Ready, David C., Van Seters, Stephen L., Lawler, Christopher P.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Yao, Kwang Bin
• Application Number:
  US08/502,087
• Time in Patent Office: 741 Days
• Field of Search: 370/85.13, 370/85.14, 370/60, 370/60.1, 370/94.1, 370/94.2, 370/94.3, 370/389, 370/390, 370/392, 370/393, 370/394, 370/395, 370/397, 370/399, 370/401, 370/402 , 370/409, 395/200.02, 395/200.2, 395/427, 395/432, 395/250, 395/200.17, 395/200.16, 395/200.06
• US Class Current: 370/392
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Abstract

An internetworking device providing enhanced packet header translation for translating the format of a header associated with a source network into a header format associated with a destination network of a different type than the source network. The device includes a memory for storing an address portion of a received packet header in a first block of buffer locations and the remainder of the received packet in a second block of buffer locations, spaced from the first block of buffer locations by a gap. The gap permits supplemental header information to be written into the buffer when necessary for translation. The device further includes a split memory, having an SRAM portion and a DRAM portion allocated to each buffer, with at least the address portion of a received packet and the gap located in the SRAM portion, so as to optimize the translation performance of the device.

Claims

1. An internetworking device for interconnecting a plurality of networks, said device comprising:

a memory comprising a plurality of buffers, each buffer assigned to a respective network and adapted for storing a packet received from said respective network, said packet including a header having an address portion; and

a buffer manager, interconnecting said plurality of networks and said memory, said buffer manager controlling storage of said packet in one of said buffers assigned to said respective network, wherein said address portion of said header is separated from a remaining portion of said packet in said buffer by a gap.

2. The internetworking device recited in claim 1 further comprising a frame processor for inserting supplemental header information into said gap.

3. The internetworking device recited in claim 1 wherein said buffer manager comprises a first register for storing a header offset value corresponding to a first location in said buffer starting at which said address portion of said header is stored and a body offset value corresponding to a second location in said buffer starting at which said remaining portion of said packet is stored.

4. The internetworking device recited in claim 1 wherein each of said buffers comprises a first portion having a first access latency and a second portion having a second access latency, longer than said first access latency.

5. The internetworking device recited in claim 4 wherein said first portion of said buffers is SRAM and said second portion of said buffers is DRAM.

6. The internetworking device recited in claim 5 wherein said gap is provided in said SRAM portion of said buffers.

7. A buffer for storing a packet received by an internetworking device from a source network prior to transmission to a destination network, said packet including a header having an address portion, comprising:

a first storage area for storing said address portion of said packet header; and

a second storage area for storing a portion of the remainder of said packet, wherein said first and second storage areas are spaced by a gap in said buffer.

8. The buffer recited in claim 7 wherein said gap is adapted to receive supplemental header information when said source network and said destination network are of different types.

9. The buffer recited in claim 7 further comprising a third storage area for storing said remainder of said packet, wherein said first and second storage areas have a first access latency and said third storage area has a second access latency, longer than said first access latency.

10. The buffer recited in claim 9 wherein said first and second storage areas are SRAM and said third storage area is DRAM.

11. A method for storing a packet having a header received by an internetworking device from a first network prior to transmission to a second network, comprising the steps of:

reading an address portion of said packet header into a first plurality of sequential locations of a buffer, starting at a header offset location; and

reading a remaining portion of said packet into a second plurality of sequential locations of said buffer, starting at a body offset location, wherein said body offset location is spaced from said header offset location to provide a gap in said buffer after said address portion and before said remaining portion of said packet.

12. The method recited in claim 11 further comprising the step of writing supplemental header information into said gap in said buffer when said first and second networks are of different types.

13. An internetworking device for interconnecting a plurality of networks, said device comprising:

a memory comprising a plurality of buffers, each buffer assigned to a respective one of said plurality of networks and adapted for storing a packet received from said respective network, said packet including a header having an address portion, wherein each of said buffers comprises a first portion having a first access latency and a second portion having a second access latency longer than said first access latency; and

a buffer manager, interconnecting said plurality of networks and said memory, said buffer manager controlling storage of said packet in one of said buffers assigned to said respective network.

14. The internetworking device recited in claim 13 wherein said first portion of each of said buffers is SRAM and said second portion of each of said buffers is DRAM.

15. The internetworking device recited in claim 14 wherein said buffer manager assigns addresses in said SRAM portion of said buffer for storing said address portion of said header.

16. The internetworking device recited in claim 13 wherein said buffer manager comprises a pair of registers, a first one of said registers storing a header offset value corresponding to a first location in said buffer starting at which said address portion of said header is stored, and a second one of said registers storing a body offset value corresponding to a second location in said buffer starting at which a remaining portion of said packet, following said address portion of said header, is stored.

17. An internetworking device for interconnecting a plurality of networks, said device comprising:

a memory comprising a plurality of buffers, each buffer assigned to a respective one of said plurality of networks and adapted for storing a packet received from said respective network, said packet including a header having an address portion, wherein each of said buffers comprises a first portion having a first access latency and a second portion having a second access latency longer than said first access latency and wherein said first portion of each of said buffers is SRAM and said second portion of each of said buffers is DRAM; and

a buffer manager, interconnecting said plurality of networks and said memory, said buffer manager controlling storage of said packet in one of said buffers assigned to said respective network, wherein said buffer manager assigns addresses in said SRAM portion of said buffer for storing said address portion of said header and wherein said buffer manager increments said assigned addresses in said SRAM portion of said buffer once said address portion of said header has been stored, so as to provide a gap in the SRAM portion of said buffer between said address portion of said header and a remaining portion of said packet, following said address portion.

18. The internetworking device recited in claim 17 further comprising a frame processor adapted for accessing said SRAM portion of said buffer to insert supplemental header information into said gap to translate said packet header into a format compatible with one of said plurality of networks of a type different than said respective network from which said packet is received.

19. A memory for storing a packet during transmission of said packet from a first network to a second network, said packet having a predetermined length and including a header having an address portion, said memory comprising:

a first memory portion having a first access latency, said first memory portion having a predetermined size and being adapted to store at least said address portion of said header; and

a second memory portion having a second access latency, longer than said first access latency and adapted to store a portion of said packet if said predetermined packet length exceeds said predetermined size of said first memory portion.

20. The memory recited in claim 19 wherein said first memory portion is SRAM and said second memory portion is DRAM.

21. The memory recited in claim 19 wherein said first memory portion is adapted to have a gap therein comprising a plurality of empty locations, wherein said gap is positioned after said address portion of said header.

22. A method for storing a packet during transmission of said packet from a first network to a second network, said packet having a predetermined length and including a header having an address portion, comprising the steps of:

storing said address portion of said header in a first portion of memory having a first access latency, said first portion of memory having a predetermined size; and

storing a portion of said packet in a second portion of memory having a second access latency, longer than said first access latency if said predetermined packet length exceeds said predetermined size of said first portion of memory.

23. The method recited in claim 22 wherein said first portion of memory is SRAM and said second portion of memory is DRAM.

24. The method recited in claim 22 further comprising the steps of:

storing said address portion of said header in a first plurality of sequential locations of said first portion of memory;

storing a remaining portion of said packet in a second plurality of sequential locations of said first portion of memory; and

spacing said first plurality of sequential locations of said first portion of memory from said second plurality of sequential locations of said first portion of memory to provide a gap between said address portion of said header and said remaining portion of said packet.

25. A method for storing a packet during transmission of said packet from a first network to a second network, said packet having a predetermined length and including a header having an address portion, comprising the steps of:

storing said address portion of said header in a first plurality of sequential locations of said first portion of memory having a first access latency, said first portion of memory having a predetermined size;

storing a remaining portion of said packet in a second plurality of sequential locations of said first portion of memory;

storing a portion of said packet in a second portion of memory having a second access latency, longer than said first access latency if said predetermined packet length exceeds said predetermined size of said first portion of memory;

spacing said first plurality of sequential locations of said first portion of memory from said second plurality of sequential locations of said first portion of memory to provide a gap between said address portion of said header and said remaining portion of said packet; and

inserting supplemental header information into said gap to convert said received packet into a packet compatible with said second network.