Apparatus and method for trellis decoder
First Claim
1. A digital data processing apparatus in which a predetermined number of bits of a portion of information symbols constituted by a plurality of bits in a transmitting side, is convolutional-coded so as to produce a plurality of coded bits, whereas a number of bits of a remaining portion of the information symbols are uncoded bits, a combination of the coded bits and the uncoded bits is trellis-coded, and the trellis-coded bits are decoded in a receiving side, so that the uncoded bits are decoded utilizing the coded bits that are decoded in a convolutional decoding portion, the apparatus comprising:
- region determining means for inputting a received symbol so as to generate at least one uncoded bit and producing regional information corresponding to a group of symbols specified by the received symbol;
delaying means for delaying the regional information output from the region determining means for as long as the received symbol is maximum-likelihood-decoded by a maximum-likelihood decoding means; and
decoding means for inputting an output from the delaying means and a coded bit that is decoded by the maximum-likelihood decoding means, and for outputting the uncoded bits as a result thereof,wherein the region determining means includes means for determining an optimal bit number in such a manner that the optimal bit number is a minimum bit number while not less than log2 J, where J indicates a number of groups for the information symbols specified by the received symbol.
1 Assignment
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Accused Products
Abstract
A digital data processing apparatus capable of reducing a circuit scale without deteriorating error-correcting capability, and capable of reducing the bit number of a branch metric calculating circuit. The apparatus includes: a region determining portion which determines an optimal bit number corresponding to the number of representative symbol groups; a delaying portion which delays an output from the region determining portion for as long as a coded bit is decoded by a Viterbi decoding portion; and a decoding portion which inputs and decodes an output from the delaying portion and a coded bit that is decoded by the Viterbi decoding portion so as to be decoded, and which outputs the uncoded bit.
27 Citations
19 Claims
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1. A digital data processing apparatus in which a predetermined number of bits of a portion of information symbols constituted by a plurality of bits in a transmitting side, is convolutional-coded so as to produce a plurality of coded bits, whereas a number of bits of a remaining portion of the information symbols are uncoded bits, a combination of the coded bits and the uncoded bits is trellis-coded, and the trellis-coded bits are decoded in a receiving side, so that the uncoded bits are decoded utilizing the coded bits that are decoded in a convolutional decoding portion, the apparatus comprising:
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region determining means for inputting a received symbol so as to generate at least one uncoded bit and producing regional information corresponding to a group of symbols specified by the received symbol; delaying means for delaying the regional information output from the region determining means for as long as the received symbol is maximum-likelihood-decoded by a maximum-likelihood decoding means; and decoding means for inputting an output from the delaying means and a coded bit that is decoded by the maximum-likelihood decoding means, and for outputting the uncoded bits as a result thereof, wherein the region determining means includes means for determining an optimal bit number in such a manner that the optimal bit number is a minimum bit number while not less than log2 J, where J indicates a number of groups for the information symbols specified by the received symbol. - View Dependent Claims (2, 3, 4)
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5. An uncoded bit decoding device in which a predetermined number of bits of a portion of information symbols constituted by a plurality of bits in a transmitting side, is Viterbi-coded so as to produce at least one coded bit, whereas a number of bits of a remaining portion of the information symbols are uncoded bits, a combination of the at least one coded bit and the uncoded bits is trellis-coded, and the trellis-coded bits are decoded in a receiving side, so that the uncoded bits are decoded utilizing the at least one coded bit that is decoded in a Viterbi decoding portion, the device comprising:
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region determining means for determining in which one of a plurality of groups each having four adjacent symbols, the received symbol is located and outputting a signal indicative of the one group; delaying means for delaying an output from the region determining means for as long as the at least one coded bit is decoded by the Viterbi decoding portion; and decoding means for inputting and decoding an output from the delaying means and the at least one coded bit that is decoded by the Viterbi decoding means, and for outputting the uncoded bits as a result thereof. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A branch metric processing apparatus where a predetermined number of bits of a portion of information symbols constituted by a plurality of bits in a transmitting side, is convolutional-coded so as to produce a plurality of coded bits, whereas a number of bits of a remaining portion of the information symbols are uncoded bits, a combination of the coded bits and the uncoded bits is trellis-coded, and the trellis-coded bits are decoded in a receiving side, so that the uncoded bits are decoded in accordance with a received symbol obtained after soft-decision, utilizing the coded bits that are decoded in a Viterbi decoding portion, the apparatus comprising:
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limiter means for performing an amplitude limitation on the received symbol obtained by the soft-decision; distance calculating means for producing a branch metric using an output of the Viterbi decoding portion, by calculating a square of Euclidean distance on data obtained from the limiter means in the form of a first number of bits; and approximation means for replacing the first number of bits by a second number of bits fewer than the first number of bits. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification