Apparatus for reducing jitter of a spectrum spread clock signal and method therefor

• US 5,651,035 A
• Filed: 04/28/1995
• Issued: 07/22/1997
• Est. Priority Date: 04/28/1995
• Status: Expired due to Fees

• Current Assignee: International Microcircuits Inc (Infineon Technologies AG)
• Original Assignee: International Microcircuits Inc (Infineon Technologies AG)
• Inventors: McCune, Earl William Jr., Tozun, Orhan
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US08/430,575
• Time in Patent Office: 816 Days
• Field of Search: 375/354, 375/371, 375/373, 375/374, 375/375, 375/376, 327/141, 327/147, 327/148, 327/156, 327/157
• US Class Current: 375/373
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal

Abstract

An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.

Claims

1. Apparatus for generating spectrum spread clock pulses, comprising:

a reference clock pulse generator that generates pulses at a reference clock frequency;

means for generating a digital signal representation of an input angle;

an accumulator connected to said reference clock and said generating means, said accumulator storing a digital signal representation of an accumulated angle in accordance with an input relationship which is given as;

##EQU2## where P is said accumulated angle;

M is said input angle;

K=2ⁿ ;

K is the state size of said accumulator; and

n is the number of binary bits stored by said accumulator;

a phase locked loop arranged to includes a loop filter and a frequency divider, said phase locked loop having an input that is driven by the most significant bit (MSB) of the output of said accumulator; and

means for removing a compensating charge from said loop filter during an overshoot interval when the output of said frequency divider differs from said MSB, wherein said overshoot interval is in accordance with a relationship which is given as;

space="preserve" listing-type="equation">Δ

T=[GT.sub.c ]/M

where Δ

T is the overshoot interval;

G=P-K/2 when the MSB changes from logic "0" to logic "1";

T_c is the period of the pulses generated by said reference clock; and

M is said input angle.

2. The apparatus of claim 1, wherein a current provided by a phase detector of said phase locked loop causes a charge to be injected into said loop filter during said overshoot interval in accordance with a relationship which is given as:

space="preserve" listing-type="equation">Q.sub.os =(i.sub.pd GT.sub.c)/M

where

Q_os is said injected charge; and

i_pd is said current provided by said phase detector.

3. The apparatus of claim 2 wherein said compensating charge is removed during an integral number of periods of said reference clock in accordance with a relationship which is given as:

space="preserve" listing-type="equation">Q.sub.x =i.sub.x (mT.sub.c)=Q.sub.os

where

Q_x is the compensating charge;

m is the number of periods of the pulses of said reference clock during which said compensating charge is removed; and

space="preserve" listing-type="equation">i.sub.x =i.sub.pd G/mM.

4. The apparatus of claim 1 wherein said generating means is connected to said reference clock and said input angle signals are provided in response to said reference clock pulses.

5. The apparatus of claim 4 wherein said generating means comprises:

a frequency divider that provides divider pulses at a frequency that is a submultiple of said reference clock frequency;

a counter that is incremented in response to a divider pulse to provide address signals; and

a programmable read only memory that is connected to said counter, said programmable memory providing said input angle signals in response to said address signals.