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High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

  • US 5,651,125 A
  • Filed: 07/10/1995
  • Issued: 07/22/1997
  • Est. Priority Date: 10/29/1993
  • Status: Expired due to Fees
First Claim
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1. A superscalar microprocessor comprising:

  • an instruction supply;

    a multiple instruction decoder, coupled to said instruction supply, for decoding multiple instructions in the same microprocessor cycle, said decoder decoding both integer and floating point instructions in the same microprocessor cycle, said decoder dispatching both decoded integer instructions and decoded floating point instructions in the same microprocessor cycle thus providing dispatched instructions;

    a data processing bus coupled to said decoder;

    an integer functional unit coupled to said data processing bus to receive dispatched instructions from the decoder;

    a floating point functional unit coupled to said data processing bus to receive dispatched instructions from the decoder;

    a branch prediction circuit coupled to said instruction supply for predicting the outcome of branch instructions thus determining predicted-taken branches including instructions which are then speculatively executed by the integer functional unit or the floating point functional unit to produce speculative results;

    a branch functional unit, coupled to said data processing bus and the branch prediction circuit, for executing branch instructions and for determining if a branch is a mispredicted branch or a correctly predicted branch;

    a common reorder buffer, coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to store said speculative results in common storage elements, said common reorder buffer renaming registers, issuing multiple instructions in a single cycle, retiring multiple instructions in a single cycle, and retiring speculative results which become non-speculative results by virtue of being in a correctly predicted branch, said common reorder buffer not retiring speculative results in mispredicted branches; and

    a common register file, coupled to said data processing bus and to said common reorder buffer, for storing non-speculative results which are retired from said common reorder buffer.

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