High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

• US 5,651,125 A
• Filed: 07/10/1995
• Issued: 07/22/1997
• Est. Priority Date: 10/29/1993
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Johnson, William M., Witt, David B.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/501,243
• Time in Patent Office: 743 Days
• Field of Search: 395/375, 395/800, 395/474, 395/306, 395/391, 395/393, 395/394
• US Class Current: 712/218
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.

Claims

1. A superscalar microprocessor comprising:

an instruction supply;

a multiple instruction decoder, coupled to said instruction supply, for decoding multiple instructions in the same microprocessor cycle, said decoder decoding both integer and floating point instructions in the same microprocessor cycle, said decoder dispatching both decoded integer instructions and decoded floating point instructions in the same microprocessor cycle thus providing dispatched instructions;

a data processing bus coupled to said decoder;

an integer functional unit coupled to said data processing bus to receive dispatched instructions from the decoder;

a floating point functional unit coupled to said data processing bus to receive dispatched instructions from the decoder;

a branch prediction circuit coupled to said instruction supply for predicting the outcome of branch instructions thus determining predicted-taken branches including instructions which are then speculatively executed by the integer functional unit or the floating point functional unit to produce speculative results;

a branch functional unit, coupled to said data processing bus and the branch prediction circuit, for executing branch instructions and for determining if a branch is a mispredicted branch or a correctly predicted branch;

a common reorder buffer, coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to store said speculative results in common storage elements, said common reorder buffer renaming registers, issuing multiple instructions in a single cycle, retiring multiple instructions in a single cycle, and retiring speculative results which become non-speculative results by virtue of being in a correctly predicted branch, said common reorder buffer not retiring speculative results in mispredicted branches; and

a common register file, coupled to said data processing bus and to said common reorder buffer, for storing non-speculative results which are retired from said common reorder buffer.

2. The microprocessor of claim 1 wherein said integer functional unit includes at least one reservation station.

3. The microprocessor of claim 1 wherein said integer functional unit includes two reservation stations.

4. The microprocessor of claim 1 wherein said floating point functional unit includes at least one reservation station.

5. The microprocessor of claim 1 wherein said floating point functional unit includes two reservation stations.

6. The microprocessor of claim 1 wherein said data processing bus includes:

a plurality of opcode buses;

a plurality of operand buses;

a plurality of instruction type buses;

a plurality of result buses; and

a plurality of result tag busses.

7. The microprocessor of claim 6 wherein said operand buses include operand tag buses.

8. The microprocessor of claim 1 wherein said data processing bus includes a plurality of operand buses and a plurality of result buses which each exhibit a predetermined first data width and wherein said common reorder buffer includes a memory for storing results exhibiting a width equal to the first data width and results exhibiting a width equal to a multiple of the first data width.

9. The microprocessor of claim 1 wherein said decoder further includes dispatching means for dispatching both integer and floating point instructions in program order.

10. The microprocessor of claim 1 wherein said floating point functional unit processes operands exhibiting multiple sizes.

11. The microprocessor of claim 1 wherein said floating point functional unit comprises a single precision/double precision floating point functional unit.

12. The microprocessor of claim 1 wherein said multiple instruction decoder is capable of decoding four instructions per microprocessor cycle.

13. The microprocessor of claim 1 further comprising:

a bus interface unit for interfacing said microprocessor an external memory in which instructions and data are stored;

an internal address data communications bus coupled to said bus interface unit;

a load/store functional unit coupled to said data processing bus to receive load and store instructions therefrom, said load/store functional unit further being coupled to said internal address data communications bus to provide said load/store functional unit access to said external memory;

an instruction cache coupled to said internal address data communications bus and said decoder to provide said decoder with a source of instructions, said instruction cache performing as the instruction supply;

a data cache coupled to said internal address data communications bus and said load/store functional unit,

said internal address data communications bus communicating address and data information among said external memory, said instruction cache and said data cache.

14. The microprocessor of claim 1 combined with an external memory for providing instructions and data to said microprocessor.

15. The microprocessor of claim 6 wherein said plurality of operand buses are buses on which both operands and operand tags are transmitted.

16. The microprocessor of claim 1 further comprising a plurality of writeback buses, coupled between the common reorder buffer and the common register file, for transferring results retired from the common reorder buffer to the common register file.

17. A superscalar microprocessor comprising:

an instruction cache for supplying instructions from a computer program including branch instructions, the instruction cache including a branch prediction unit for predicting the outcome of branch instructions thus determining predicted-taken branches which include speculative instructions to be speculatively executed;

a multiple instruction decoder, coupled to the instruction cache, for decoding multiple instructions in the same microprocessor cycle, said decoder decoding both integer and floating point instructions in the same microprocessor cycle, said decoder dispatching both decoded integer instructions and decoded floating point instructions in the same microprocessor cycle thus providing dispatched instructions;

a data processing bus coupled to said decoder;

an integer functional unit coupled to said data processing bus to receive dispatched instructions from the decoder as speculative instructions, said integer functional unit including a plurality of reservation stations for enabling out-of-order instruction execution by said microprocessor, said integer functional unit speculatively executing said speculative instructions when said speculative instructions are integer instructions thus producing speculative results;

a floating point functional unit coupled to said data processing bus to receive dispatched instructions from the decoder as speculative instructions, said floating point functional unit including a plurality of reservation stations for enabling out-of-order instruction execution by said microprocessor, said floating point functional unit speculatively executing said speculative instructions when said speculative instructions are floating point instructions thus producing speculative results;

a branch functional unit coupled to said data processing bus for executing branch instructions and for determining if a branch is a mispredicted branch or a correctly predicted branch;

a common reorder buffer, coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to store said speculative results in common storage elements to enable instructions to be processed speculatively and out-of-order, said reorder buffer renaming registers, issuing multiple instructions in a single cycle, retiring multiple instructions in a single cycle, and deallocating speculative results when such speculative results are in a mispredicted branch, said reorder buffer retiring those results whose status changes from speculative to non-speculative as a consequence of being in a correctly predicted branch;

a common register file coupled to said data processing bus and to said common reorder buffer for storing results which are retired from said common reorder buffer;

retire logic, coupled to the common register file, for monitoring the status of results in the common reorder buffer to determine when the status of results in the common reorder buffer changes from speculative to non-speculative as a consequence of being in a correctly predicted branch; and

a load/store functional unit coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to permit loading and storage of information.

18. The microprocessor of claim 17 wherein said data processing bus includes:

a plurality of opcode buses;

a plurality of operand buses;

a plurality of instruction type buses;

a plurality of result buses; and

a plurality of result tag busses.

19. The microprocessor of claim 17 wherein said operand buses include operand tag buses.

20. The microprocessor of claim 17 wherein said data processing bus includes a plurality of operand buses and a plurality of result buses which each exhibit a predetermined first data width and wherein said common reorder buffer includes a memory for storing results exhibiting a width equal to the first data width and results exhibiting a width equal to a multiple of the first data width.

21. The microprocessor of claim 17 wherein said decoder further includes dispatching means for dispatching both integer and floating point instructions in program order.

22. The microprocessor of claim 17 wherein said floating point functional unit processes operands exhibiting multiple sizes.

23. The microprocessor of claim 17 wherein said floating point functional unit comprises a single precision/double precision floating point functional unit.

24. The microprocessor of claim 17 wherein said multiple instruction decoder is capable of decoding four instructions per microprocessor cycle.

25. The microprocessor of claim 17 further comprising:

a bus interface unit for interfacing said microprocessor to an external memory in which instructions and data are stored;

an internal address data communications bus coupled to said bus interface unit;

said instruction cache being coupled to said internal address data communications bus and said decoder to provide said decoder with a source of instructions;

a data cache coupled to said internal address data communications bus and said load/store functional unit,

said internal address data communications bus communicating address and data information among said external memory, said instruction cache and said data cache.

26. The microprocessor of claim 17 combined with an external memory for providing instructions and data to said microprocessor.

27. The microprocessor of claim 18 wherein said plurality of operand buses are buses on which both operands and operand tags are transmitted.

28. The microprocessor of claim 17 further comprising a plurality of writeback buses, coupled between the common reorder buffer and the common register file, for transferring results retired from the common reorder buffer to the common register file.