Method for making thin film transistors for a liquid crystal display

• US 5,652,158 A
• Filed: 09/05/1996
• Issued: 07/29/1997
• Est. Priority Date: 11/29/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Bae, Byung Seong
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/708,760
• Time in Patent Office: 327 Days
• Field of Search: 437/40 TFT, 437/41 TFT, 437/51, 437/21, 437/913, 437/50, 148/DIG. 150
• US Class Current: 438/30
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A method of manufacturing thin film transistors for use in a liquid crystal display which reduces the failures due to excessive leakage current. A silicon layer, first insulating layer, and gate electrode layer are serially formed over a transparent substrate. The gate electrode layer is patterned to form a plurality of gate electrodes and associated pairs of gate line electrodes, and the silicon layer is patterned into thin-film transistor regions. Then, a relatively thick second insulating layer is formed over the substrate, and contact holes are formed in the second insulating layer. Finally, a metal layer is formed and patterned over the second insulating layer and through the contact holes to connect each gate electrode with its associated pair of gate line electrodes; and to form source and drain electrodes. The thick second insulating layer provides increased spacing between the thin-film transistors and the associated gate interconnects, thereby reducing leakage current and failures due to excessive leakage current.

Claims

1. A method of manufacturing thin film transistor for use in a liquid crystal display, comprising the steps of:

providing a transparent substrate;

forming a silicon layer over the substrate;

forming a first insulating layer over the silicon layer, said first insulating layer having a first predetermined thickness;

forming a gate electrode layer over the first insulating layer;

patterning the gate electrode layer to form a plurality of substantially parallel, linear, and non-contiguous gate lines having a first width, each said gate line comprising an associated pair of gate line electrodes each separated by a predetermined distance from a gate electrode positioned therebetween;

patterning the silicon layer into a plurality of thin-film transistor regions;

forming a source region and a drain region in each said thin-film transistor region;

forming a second insulating layer over the plurality of gate electrodes and the associated pairs of gate line electrodes, said second insulating layer having a second predetermined thickness greater than said first predetermined thickness;

selectively forming a plurality of first contact holes through the second insulating layer to expose a portion of the plurality of gate electrodes and the associated pairs of gate line electrodes; and

,

forming a plurality of metal lines having a second width, each said metal line ohmically connected through the first contact holes to the gate electrode and the associated pair of gate line electrodes within a gate line.

2. The method of claim 1, in which the second width is less than the first width.

3. The method of claim 2, further comprising the steps of:

selectively forming a plurality of second contact holes in the second insulating layer to expose portions of the source and drain regions; and

,

forming source and drain electrodes through the plurality of second contact holes, whereby said source and drain electrodes are ohmically connected to said source and drain regions, respectively.

4. The method of claim 3, wherein said source and drain electrodes are formed substantially orthogonal to said gate lines.

5. The method of claim 4, wherein said gate lines are polysilicon.

6. The method of claim 5, wherein said first insulating layer is formed by a thermal oxide process.

7. The method of claim 5, wherein said first insulating layer is formed by a chemical vapor deposition process.

8. A method of manufacturing a thin film transistor for use in a liquid crystal display, comprising the steps of:

providing a transparent substrate;

forming a silicon layer over the substrate;

forming a first insulating layer over the silicon layer, said first insulating layer having a first predetermined thickness;

forming a gate electrode layer over the first insulating layer;

patterning the gate electrode layer to form a plurality of substantially parallel, linear, and non-contiguous gate lines having a first width, each said gate line comprising an associated pair of gate line electrodes each separated by a predetermined distance from a gate electrode positioned therebetween;

patterning the silicon layer into a plurality of thin-film transistor regions;

forming a source region and a drain region in each said thin-film transistor region;

forming a second insulating layer over the substrate, the plurality of thin-film transistor regions, and the plurality of gate lines, said second insulating layer having a second predetermined thickness greater than said first predetermined thickness;

selectively forming a plurality of first and second contact holes through the second insulating layer, whereby said plurality of first contact holes expose portions of the plurality of gate electrodes and the associated pairs of gate line electrodes, and said plurality of second contact holes expose portions of said source and drain regions; and

,

forming a plurality of first and second metal lines over said second insulating layer and in said plurality of first and second contact holes, respectively, whereby each said first metal line has a second width and is ohmically connected through the first contact holes to the gate electrode and the associated pair of gate line electrodes within a gate line, and said plurality of second metal lines comprise source and drain electrodes which are ohmically connected through said second contact holes to said source and drain regions, respectively.

9. The method of claim 8, wherein said source and drain electrodes are formed substantially orthogonal to said gate lines.

10. The method of claim 9, wherein said gate lines are polysilicon.

11. The method of claim 10, wherein said first insulating layer is formed by a thermal oxide process.

12. The method of claim 10, wherein said first insulating layer is formed by a chemical vapor deposition process.

13. A method of manufacturing a thin film transistor for use in a liquid crystal display, comprising the steps of:

providing a transparent substrate;

forming a silicon layer over the substrate;

forming a first insulating layer over the silicon layer, said first insulating layer having a first predetermined thickness;

forming a gate electrode layer of polysilicon over the first insulating layer;

patterning the gate electrode layer to form a plurality of substantially parallel, linear, and non-contiguous gate lines having a first width, each said gate line comprising an associated pair of gate line electrodes each separated by a predetermined distance from a gate electrode positioned therebetween;

patterning the silicon layer into a plurality of thin-film transistor regions;

forming a source region and a drain region in each said thin-film transistor region;

forming a second insulating layer over the substrate, the plurality of thin-film transistor regions, and the plurality of gate lines, said second insulating layer having a second predetermined thickness of approximately 4000 to 6000 angstroms;

selectively forming a plurality of first and second contact holes through the second insulating layer, whereby said plurality of first contact holes expose portions of the plurality of gate electrodes and the associated pairs of gate line electrodes, and said plurality of second contact holes expose portions of said source and drain regions; and

,

forming, substantially orthogonal to said gate lines, a plurality of first and second metal lines over said second insulating layer and in said plurality of first and second contact holes, respectively, whereby each said first metal line has a second width less than said first width and is ohmically connected through the first contact holes to the gate electrode/and the associated pair of gate line electrodes within a gate line, and said plurality of second metal lines comprise source and drain electrodes which are ohmically connected through said second contact holes to said source and drain regions, respectively.