Built-in load board design for performing high resolution quiescent current measurements of a device under test

• US 5,652,524 A
• Filed: 10/24/1995
• Issued: 07/29/1997
• Est. Priority Date: 10/24/1995
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Scorsone, Joseph J., Fell, Joseph H. III, Selby, Paul H. III, Jennion, Mark W.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/547,265
• Time in Patent Office: 644 Days
• Field of Search: 324/73.1, 324/158.1, 324/765, 371/22.1, 371/22.5, 371/22.6, 371/15.1, 371/25.1, 437/8, 365/201
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/2801 Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] G01R31/318508 takes precedence; contactless testing G01R31/302; testing contacts or connections G01R31/66
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

An improved load board design having a generic test circuit integrated into the load board capable of functioning with varying devices under test and requires little to no wiring. The test circuit is located in a fixed and optimal position of the load board with relation to the DUT. In a preferred embodiment, the test circuit is a quiescent test circuit for interfacing an integrated circuit tester to the DUT. The quiescent test circuit is capable of supplying high powered voltage to a DUT while the DUT'"'"'s desired internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously deselecting the high-powered voltage supply to the DUT and selecting the integrated circuit tester'"'"'s parametric measurement unit for powering the DUT. The integrated circuit tester, through a parametric measurement unit is capable of measuring the quiescent current of the DUT, while powering the DUT.

Claims

1. A load board having multi-level signal and power planes, for coupling pins of an integrated circuit device under test (DUT) to a conventional integrated circuit tester, comprising:

said load board having at least two separated portions each having a plurality of signal and power planes,

a quiescent test circuit mounted on and integrated with a first portion of said multi-level load board such that said quiescent test circuit is contained on and electrically connected to its multilevel signal and power planes,

said load board having means for mounting the device under test (DUT) on a second portion of multi-level load board and for connecting said DUT to its multi-level signal and plural power planes,

said quiescent test circuit having means for coupling the integrated circuit tester to the integrated circuit device under test (DUT), and

said quiescent test circuit having means for switching a low power level to one of said plural power planes of said second portion of said multi-lever load board to allow the integrated circuit test to selectably measure quiescent current consumption of the integrated circuit device under test.

2. The load board of claim 1, wherein said quiescent test circuit has a first input terminal coupled to a plural current level power supply and a second input terminal coupled to the integrated circuit tester, and

one output terminal coupled to the integrated circuit device under test;

and

wherein said quiescent test circuit is operable to select one of said plural current levels to be received at said output terminal.

3. The load board of claim 2, wherein said load board of claim 2, wherein said plural current level power supply provided at said first input terminal are electrically isolated from each other.

4. The load board of claim 2, wherein said integrated circuit tester controls which of said power levels is to be received at said output terminal.