Burst EDO memory device having pipelined output buffer

• US 5,652,724 A
• Filed: 02/10/1995
• Issued: 07/29/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/386,563
• Time in Patent Office: 900 Days
• Field of Search: 365/189.05, 365/233, 365/238.5, 326/82, 326/83
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. A two stage pipelined output buffer latches read data in a first stage while data from a second stage is driven from the device. Internal read lines may become invalid in preparation for additional access cycles after the data is latched in the first stage. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Claims

1. A circuit to drive an output data signal from a memory device, comprising:

an output driver circuit having a driver control input; and

a latch adapted to receive a latch control signal and a clear signal;

said latch further adapted to receive an internal data signal and drive the driver control input in response to a first state of the latch control signal despite transitions of the clear signal;

said latch further adapted to store the internal data signal and drive the driver control input in response to a second state of the latch control signal and a first state of the clear signal;

said latch being cleared in response to the second state of the latch control signal and a second state of the clear signal.

2. The circuit of claim 1, wherein the clear control signal clears said latch between cycles in a burst access of the memory device.

5. The circuit of claim 1, wherein said output driver circuit provides a high impedance output from the memory device when said latch is cleared.

6. The circuit of claim 1, wherein said latch after being cleared, remains cleared while the latch control signal is in the second state, despite transitions of the clear control signal.

7. The circuit of claim 1, wherein the first state of the latch control signal is a low voltage level, and the first state of the first state of the clear signal is a high voltage level.

8. The circuit of claim 1, wherein the latch comprises:

a feedback circuit coupled to the driver control input and the latch control signal; and

switching circuitry connected to the feedback circuit and the latch control signal for coupling a feedback signal to the input of the latch in response to the latch control signal.

9. The circuit of claim 8 wherein the feedback circuit comprises a NOR gate having a first input coupled to the driver control input, a second input connected to the clear signal, and an output connected to the switching circuity.

10. The circuit of claim 1, wherein the output driver circuit comprises:

a driver transistor having a gate connected to the driver control input and a drain connected to an output.

3. A circuit to drive an output data signal from a memory device, comprising:

an output driver circuit having a driver control input; and

a latch adapted to receive a latch control signal and a clear signal, said latch further adapted to receive an internal data signal and drive the driver control input in response to a first state of the latch control signal, said latch further adapted to store the internal data signal and drive the driver control input in response to a second state of the latch control signal and a first state of the clear signal, said latch being cleared in response to the second state of the latch control signal and a second state of the clear signal,

an output feedback switching circuit to feed the driver control input back to an input of said latch, when the latch control signal is in the second state, to form said latch; and

an internal data switching circuit to isolate the internal data signal from the input of said latch when said output feedback switching circuit is feeding the driver control input back to the input of said latch.

4. The circuit of claim 3, wherein said latch after being cleared, remains cleared until the internal data signal is presented on the input of said latch.