Burst EDO memory device having pipelined output buffer
First Claim
1. A circuit to drive an output data signal from a memory device, comprising:
- an output driver circuit having a driver control input; and
a latch adapted to receive a latch control signal and a clear signal;
said latch further adapted to receive an internal data signal and drive the driver control input in response to a first state of the latch control signal despite transitions of the clear signal;
said latch further adapted to store the internal data signal and drive the driver control input in response to a second state of the latch control signal and a first state of the clear signal;
said latch being cleared in response to the second state of the latch control signal and a second state of the clear signal.
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Accused Products
Abstract
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. A two stage pipelined output buffer latches read data in a first stage while data from a second stage is driven from the device. Internal read lines may become invalid in preparation for additional access cycles after the data is latched in the first stage. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
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Citations
10 Claims
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1. A circuit to drive an output data signal from a memory device, comprising:
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an output driver circuit having a driver control input; and a latch adapted to receive a latch control signal and a clear signal;
said latch further adapted to receive an internal data signal and drive the driver control input in response to a first state of the latch control signal despite transitions of the clear signal;
said latch further adapted to store the internal data signal and drive the driver control input in response to a second state of the latch control signal and a first state of the clear signal;
said latch being cleared in response to the second state of the latch control signal and a second state of the clear signal. - View Dependent Claims (2, 5, 6, 7, 8, 9, 10)
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3. A circuit to drive an output data signal from a memory device, comprising:
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an output driver circuit having a driver control input; and a latch adapted to receive a latch control signal and a clear signal, said latch further adapted to receive an internal data signal and drive the driver control input in response to a first state of the latch control signal, said latch further adapted to store the internal data signal and drive the driver control input in response to a second state of the latch control signal and a first state of the clear signal, said latch being cleared in response to the second state of the latch control signal and a second state of the clear signal, an output feedback switching circuit to feed the driver control input back to an input of said latch, when the latch control signal is in the second state, to form said latch; and an internal data switching circuit to isolate the internal data signal from the input of said latch when said output feedback switching circuit is feeding the driver control input back to the input of said latch. - View Dependent Claims (4)
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Specification