Signature analysis usage for fault isolation

• US 5,652,754 A
• Filed: 12/27/1995
• Issued: 07/29/1997
• Est. Priority Date: 12/27/1995
• Status: Expired due to Fees

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Electronics Corporation (AT&T, Inc.)
• Inventors: Pizzica, Stephen V.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US08/579,523
• Time in Patent Office: 580 Days
• Field of Search: 371/22.4, 371/22.5, 371/26, 371/23, 371/25.1, 371/27, 371/67.1, 395/183.09, 395/183.16, 395/183.2, 395/184.01
• US Class Current: 714/732
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

Test equipment and test methods employing signature analysis to achieve fault isolation of digital modules. Fault free signatures and faulty signatures of a digital module are stored in a lookup table that are derived from physical measurement or simulation of all components thereof. Test input signals are then applied to a digital module under test, and outputs and test points thereof are applied to a multiple input shift register signal analyzer. The multiple input shift register signal analyzer performs pass/fail signature analysis using the applied signals. Test inputs from a source (either on-board the module or external thereto) are applied to the digital module under test. When a failure occurs during testing of the digital module under test, comparator circuitry is used to find a corresponding signature match with the stored faulty signatures. A message is then sent as an output from the comparator circuitry identifying the failed node so that the digital module under test can be repaired. The present invention does not require expensive automatic test equipment and therefore provides a more cost-effective approach to failure analysis.

Claims

1. A test method for providing fault isolation of digital module circuitry under test that comprises a plurality of test signal inputs for receiving test input signals, a plurality of signal outputs, and a plurality of test points, said test method comprising steps of:

recording a fault free signature of a functional digital module that comprises circuitry that is substantially identical to the digital module circuitry under test;

shorting and opening every node of the functional digital module with test input signals applied to signal inputs thereof;

applying output signals of the functional digital module to a multiple input shift register and signature analyzer and recording signal outputs from said multiple input shift register and signature analyzer in a memory lookup table, which recorded signal outputs correspond to recorded failure signatures of the functional digital module;

testing the digital module circuitry under test;

comparing failure signatures that occur during testing of the digital module circuitry under test with the recorded failure signatures derived from the functional digital module; and

correlating the failed signatures to a specific node failure to generate a fault isolation output signal for the digital module circuitry under test.

2. The test method claim 1 wherein the step of shorting and opening every node of the functional digital module comprises the step of physically shorting and opening every node thereof with test inputs applied to the signal inputs thereof.

3. The test method claim 1 wherein the step of shorting and opening every node of the functional digital module comprises the step of shorting and opening by simulation every node with test inputs applied to the signal inputs thereof.

4. Test equipment for providing fault isolation of digital module circuitry under test, said digital module circuitry under test having a plurality of test signal inputs for receiving test input signals, a plurality of output signals, and a plurality of test points, said test equipment comprising:

a multiple input shift register signature analyzer coupled to received signals derived from output signals and module test points both of a functional digital module and of the digital module circuitry under test;

a memory lookup table for storing a fault free signature from the functional digital module and faulty signatures derived from shorting and opening each node of the digital module circuitry under test; and

a comparator and correlator coupled to the multiple input shift register signature analyzer and to the memory lookup table for comparing faulty signatures that occur during testing of the digital module circuitry under test with the stored fault free signatures and for correlating failed signals to a specific node to generate and output a failed node message.