Devices and systems with conditional instructions

• US 5,652,910 A
• Filed: 06/07/1995
• Issued: 07/29/1997
• Est. Priority Date: 05/04/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Boutaud, Frederic, Ehlig, Peter N.
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/477,975
• Time in Patent Office: 783 Days
• Field of Search: 395/800, 395/375, 395/860
• US Class Current: 712/218
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/323 for indirect branch instructions

Abstract

A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.

Claims

1. A data processing device or system, comprising:

an analog-to-digital converter;

an electronic processor with an instruction pipeline connected to said analog-to-digital processor;

means for decoding a conditional execution instruction within said instruction pipeline;

means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;

means for executing said set of conditioned instructions without flushing said instruction pipeline; and

wherein means for conditioning further comprise;

means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions;

means for determining which values are required by said conditional execution instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values; and

means for allowing normal execution of said conditioned instructions based on a logical combination of said mask bits and said status bits.

2. The data processing system of claim 1 further comprising an instruction memory connected to said electronic processor.

3. The data processing system of claim 1 further comprising a video output circuit connected to said electronic processor and a video display connected to said video output circuit.

4. The device or system of claim 1, wherein said means for executing further comprises:

means for executing said set of conditioned instructions in a normal manner if said condition specified in said conditional instruction is present, or by changing said conditioned instructions to a no-operation (NOP) instruction if said condition specified in said conditional instruction is not present.

5. A data processing device or system, comprising:

an analog-to-digital converter;

an electronic processor with an instruction pipeline connected to said analog-to-digital processor;

means for decoding a conditional execution instruction within said instruction pipeline;

means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;

means for executing said set of conditioned instructions without flushing said instruction pipeline; and

wherein means for conditioning further comprise;

means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions;

means for determining which values are required by said conditional execution instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values;

means for making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; and

means for comparing an actual value each of said selected status conditions to a predetermined value contained in corresponding said status bit of the conditional execution instruction.

6. A data processing device or system, comprising:

an analog-to-digital converter;

an electronic processor with an instruction pipeline connected to said analog-to-digital processor;

means for decoding a conditional execution instruction within said instruction pipeline;

means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;

means for executing said set of conditioned instructions without flushing said instruction pipeline;

wherein said conditional execution instruction includes a pair of bits corresponding to each of said status conditions of said set of predetermined status conditions;

wherein means for conditioning further comprise;

means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions; and

wherein said means for determining which status conditions further comprises,

means for using a first of said pair of bits as said mask bit for determining whether to consider a status condition; and

means for using a second of said pair of bits as a level to test said actual value of said status condition against.