Versatile memory controller chip for concurrent input/output operations

• US 5,652,912 A
• Filed: 11/28/1990
• Issued: 07/29/1997
• Est. Priority Date: 11/28/1990
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Martin Marietta Corporation
• Inventors: Lofgren, John D., Benton, Richard W.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US07/618,986
• Time in Patent Office: 2,435 Days
• Field of Search: 395/250, 395/425, 364/DIG. 1, 364/239, 364/239.51, 364/239.3, 364/521, 340/725, 340/740, 340/721, 365/189.05, 365/189.04, 365/230.03
• US Class Current: 710/21
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

A memory controller includes an input data path and an output data path. First circuitry generates signals to put the input data into at least one variably-dimensioned logical array of memory cells of a memory. Second circuitry generates signals to extract from the memory the contents of at least one variably-dimensioned logical array of memory cells. The memory may be double buffered such that data input to one of the portions may take place simultaneously as data output from the other of the portions. In a preferred embodiment, any combination of up to 254 total variable-dimensioned logical arrays of memory cells may be defined for input to and output from the memory. The memory controller may be viewed as supporting two simultaneous processes, an input "windowing" process for receiving windows of data and an output "windowing" process for simultaneously passing out windows of data. The memory controller is preferably realized in the form of a monolithic integrated circuit employing "bit-slice" architecture and is static and dynamic RAM-compatible.

Claims

1. Memory controller means for controlling a memory that comprises a plurality of individually addressable memory cells, the memory controller means comprising:

input data path means for receiving input data;

first means for generating signals to put said input data into at least one logical input array of memory cells of said memory, the logical input array having at least two variable input array dimensions;

second means for generating signals to extract from said memory the contents of at least one logical output array of memory cells, the logical output array having at least two variable output array dimensions that are independent of the variable input array dimensions;

output data path means for outputting as output data said contents; and

command store means for storing a plurality of input array commands and a plurality of output array commands, each of the input and output array commands defining, respectively, the input and output array dimensions of said respective logical input and output arrays of memory cells.

2. The memory controller means of claim 1 wherein said first means for generating signals and said second means for generating signals are active for accessing said memory simultaneously.

3. The memory controller means of claim 2 wherein said first means generates signals to put said input data into a variable plurality of said logical input arrays of memory cells in said memory.

4. The memory controller means of claim 3 wherein said second means generates signals to extract from said memory the contents of a variable plurality of said logical output arrays of memory cells.

5. The memory controller means of claim 4 further comprising switch means for effectively reversing the roles of said input and output arrays by interchanging the signals generated by said first and second means.

6. The memory controller means of claim 4 further comprising a first clock input means for clocking said input data and a second clock input means independent of said first clock input means,. for clocking said output data.

7. The memory controller means of claim 4 wherein said input data path means comprises demultiplexing means for decreasing the data rate while increasing the data width of said input data and wherein said output data path means comprises multiplexing means for increasing the data rate while decreasing the data width of said output data.

8. The memory controller means of claim 4 wherein said first and second means for generating signals each is capable of generating control signals for both a type of memory requiring data refresh and a type of memory not requiring data refresh, according to the type of said memory being controlled.

9. The memory controller means of claim 4 wherein said first and second means for generating signals each is programmable in order to generate control signals for a type of memory requiring data refresh according to a variable refresh rate.

10. The memory controller means of claim 4 wherein said first means is capable of generating signals to put interlaced image input data into a variable plurality of said logical input arrays of memory cells in non-interlaced format.

11. The memory controller means of claim 4 wherein said second means is programmable to extract the contents of a succeeding logical output array of memory cells a programmed time after extracting the contents of a preceding logical output array of memory cells, and to extract a succeeding row of each of said logical output arrays of memory cells a programmed time after extracting a preceding row thereof.

12. The memory controller means of claim 4 wherein said first means and said second means each comprises:

command control means for generating addresses for said command store means and for registering commands received from said command store means; and

memory address generator means, responsive to said command control means, for generating addresses for said memory to put said input data into said logical input arrays of memory cells and to extract said contents of said logical output arrays of memory cells of said memory.

13. The memory controller means of claim 12 wherein said first means and said second means each further comprises memory control signal generator means responsive to said memory address generator means for generating control signals for said memory.

14. The memory controller means of claim 13 wherein said first means and said second means each further comprises:

refresh control means, cooperatively interfaced with said memory address generator means, for performing data refresh of said memory, and

selector means, responsive to said memory address generator means, said refresh control means, and said memory control signal generator means, for selecting an address supplied by one of said memory address generator means and said refresh control means for application to said memory.

15. The memory controller means of claim 14 wherein said selector means comprises dual selectors each responsive to outputs of said memory address generator means and said memory control signal generator means of said first means and said memory address generator means and said memory control signal generator means of said second means, to apply the outputs of said memory address generator means and said memory control signal generator means of one of said first and second means to a respective one of said arrays of said memory.

16. The memory controller means of claim 15 further comprising chip control means, cooperatively interfaced with said command control means of said first means and said command control means of said second means, for outputting command addresses to said command store.

17. The memory controller means of claim 12 wherein said command store is double buffered such that one portion of said command store is capable of having commands stored therein at the same time as another portion of said command store is supplying commands to said command control means.

18. The memory controller means of claim 4, fabricated in the form of a monolithic integrated circuit.

19. The memory controller means of claim 18, bit-slice architectured such that a master memory controller means is capable of controlling one or more slave memory controller means.

20. The memory controller means of claim 19, wherein the size of the bit-slice is 10 bits.

21. Memory controller means for controlling a double-buffered memory that comprises a plurality of individually addressable memory cells, the memory controller means comprising:

input data path means for receiving input data;

first means for generating first signals to put said input data into at least one logical input array of memory cells of said memory, the logical input array having at least two variable input array dimensions;

second means for generating second signals to extract from said memory the contents of at least one logical output array of memory cells simultaneously as said first means generates said first signals, the logical output array having at least two variable output array dimensions that are independent of the variable input array dimensions; and

output data path means for outputting said contents.

22. A data transformer, comprising:

a double-buffered memory comprising a plurality of individually addressable memory cells;

means for inputting data into one or more input sub-arrays of memory cells of said memory, the input sub-arrays having at least two variable input sub-array dimensions; and

means for simultaneously extracting data from one or more output sub-arrays of memory cells of said memory different from said input sub-arrays, the output sub-arrays having at least two variable output sub-array dimensions that are independent of the variable input sub-array dimensions.

23. A general-purpose frame interface node, comprising:

a double-buffered frame memory;

means for inputting image data as one or more frames or sub-frames of at least two freely-selectable input dimensions into said memory according to commands contained in a rewritable command store; and

means for simultaneously extracting one or more frames or sub-frames of at least two freely-selectable output dimensions from said memory according to commands contained in said rewritable command store.

24. A method of controlling a memory that comprises a plurality of individually addressable memory cells, the method comprising the steps of:

receiving input data;

generating signals to put said input data into at least one logical input array of memory cells of said memory, the logical input array having at least two variable input array dimensions;

generating signals to extract from said memory the contents of at least one logical output array of memory cells, the logical output array having at least two variable output array dimensions that are independent of the variable input array dimensions;

outputting said contents as output data; and

generating addresses to retrieve a plurality of input array commands and a plurality of output array commands from command store means, and generating signals for registering said input and output array commands received from said command store means, each of said input and output array commands defining, respectively, the input and output array dimensions of said respective logical input and output arrays of memory cells.

25. A method of controlling a double-buffered memory that comprises a plurality of individually addressable memory cells, comprising the steps of:

receiving input data;

generating first signals to put said input data into at least one logical input array of memory cells of said memory, the logical input array having at least two variable input array dimensions;

generating second signals to extract from said memory the contents of at least one logical output array of memory cells simultaneously as said first means generates said first signals, the logical output array having at least two variable output array dimensions that are independent of the variable input array dimensions; and

outputting said contents.