Method of making a tester surface with high density probe points

• US 5,654,127 A
• Filed: 06/07/1995
• Issued: 08/05/1997
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US08/483,248
• Time in Patent Office: 790 Days
• Field of Search: 430/311, 430/313, 430/315, 430/318, 430/320, 430/396
• US Class Current: 430/315
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A method of making a tester surface comprising the steps of:

providing a substrate having a principal surface and a secondary surface opposite the principal surface;

forming a plurality of cavities in the substrate each extending from the principal surface to a depth in the substrate;

lining the cavities and covering the principal surface with a first layer of a flexible material;

providing a first layer of metal on the first layer of flexible material, including portions of the first layer of flexible material lining the cavities;

forming a second layer of a flexible material over the principal surface and overlying the first layer of metal;

removing a portion of the substrate extending from the secondary surface toward the principal surface so as to expose a portion of the first layer of flexible material at the depth of the cavities;

removing the exposed portion of the first layer of flexible material, so as to expose a portion of the first layer of metal;

forming a metal tip on the exposed portion of the first layer of metal; and

removing the remaining portion of the substrate.

2. The method of claim 1 wherein the second layer of flexible material is formed to substantially fill the cavities and further comprising the step of forming a second layer of metal over a portion of the second layer of flexible material extending over the principal surface.

3. The method of claim 1, further comprising, after the step of forming the second layer of flexible material, the step of forming a body of metal in the depth of the cavity.

4. The method of claim 1 wherein the step of forming the plurality of cavities comprises:

providing a computer data base for determining a location where each cavity is to be formed in the substrate;

forming an etch mask on the principal surface of the substrate from the locations in the database; and

etching exposed positions of the principal surface of the substrate.

5. The method of claim 1 further comprising the step, after the step of forming the second layer of flexible material, of bonding the tester surface to a support plate.

6. The method of claim 1 wherein the metal tip is formed of a refractory metal.

7. The method of claim 1 wherein the metal tip is formed by electroplating.

8. The method of claim 1 wherein the metal tip is formed by the steps of:

applying a first resist layer over the exposed portion of the first layer of metal;

patterning the first resist layer to form an opening therein around the exposed portion of the first layer of metal;

depositing metal within said opening in the first resist layer.

9. The method of claim 8 further comprising the step, after the step of applying the first resist layer, of applying a second resist layer over the first resist layer, wherein the second resist layer is harder than the first resist layer.

10. The method of claim 1 further comprising the step of electroplating the metal tip.

11. The method of claim 1 wherein the first layer of flexible material comprises silicon dioxide.

12. The method of claim 1 wherein the first layer of flexible material is formed by chemical vapor deposition.

13. The method of claim 1 wherein the second layer of flexible material comprises silicon dioxide.

14. The method of claim 1 wherein the second layer of flexible material is formed by chemical vapor deposition.

15. The method of claim 1 wherein the first layer of metal comprises tungsten.

16. The method of claim 1 wherein the first layer of metal is provided by chemical vapor deposition.