Die sorter

• US 5,654,204 A
• Filed: 07/20/1994
• Issued: 08/05/1997
• Est. Priority Date: 07/20/1994
• Status: Expired due to Term

• Current Assignee: Advantest Corporation
• Original Assignee: James Anderson
• Inventors: Anderson, James C.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/277,860
• Time in Patent Office: 1,112 Days
• Field of Search: 437/7, 437/8, 437/226, 437/924
• US Class Current: 438/15
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.

Claims

1. A method of manufacture for a semiconductor integrated circuit comprising the steps of:

providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being substantially untested;

separating each of said semiconductor integrated circuits from said fabricated wafer; and

probing each of said semiconductor integrated circuits.

2. The method of claim 1 further comprising the step of testing each of said semiconductor integrated circuits.

3. The method of claim 2 further comprising the step of assembling each of said semiconductor integrated circuits after said testing step.

4. The method of claim 1 further comprising the step of aligning each of said semiconductor integrated circuits to an interface means before said probing step.

5. The method of claim 4 wherein said interface means comprises a probe card comprising probes.

6. The method of claim 4 wherein said aligning step comprises a pre-aligning step and a fine alignment step of said semiconductor integrated circuit.

7. The method of claim 1 wherein said separating step comprises a sawing step.

8. The method of claim 2 further comprising a step of categorizing each of said tested semiconductor integrated circuits.

9. The method of claim 8 wherein said categorizing step separates each of said semiconductor integrated circuits into die binning group consisting essentially of a fast die, a slow die, and a reject die.

10. The method of claim 8 further comprising a step of placing each of said categorized semiconductor integrated circuits onto separate frames.

11. A method of manufacture for a semiconductor integrated circuit comprising the step of testing a semiconductor integrated circuit by use of a die sorter.

12. The method of claim 11 wherein said testing step comprises a step of probing said semiconductor integrated circuit, said semiconductor integrated circuit being separated from a semiconductor wafer.

13. The method of claim 11 further comprising a step of:

separating said semiconductor integrated circuit from a semiconductor wafer; and

providing said semiconductor integrated circuit to said die sorter.

14. The method of claim 11 further comprising a step of assembling and semiconductor integrated circuit.

15. A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of:

providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said plurality of semiconductor integrated circuits being untested; and

entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.

16. The method of claim 15 further comprising a step of retrieving said information of said fabricated wafer from a computer network before said entering step.

17. The method of claim 15 wherein said memory comprises a memory of said wafer saw.

18. The method of claim 15 wherein said memory comprises a touch boat memory device.

19. The method of claim 15 wherein said retrieving step occurs through manual data entry and network capability.

20. The method of claim 15 wherein said information comprises wafer identification.

21. The method of claim 20 wherein said wafer identification can be selected from a group of information consisting essentially from a planarization characteristic, a device size, test results, and a product name.

22. The method of claim 15 further comprising a step of entering said information of said fabricated wafer from a group of interface means consisting essentially of a keyboard, a bar-code, and keyboard/bar-code combination.

23. The method of claim 15 further comprising a step of:

sawing said fabricated wafer to separate each of said semiconductor integrated circuits;

recognizing a wafer pattern from said semiconductor integrated circuit;

storing said wafer pattern on a memory means; and

retrieving said wafer pattern at a die prober apparatus.

24. The method of claim 23 further comprising a step of using said wafer pattern to align said semiconductor integrated circuit.

25. A method of set-up for a probe card comprising the steps of:

providing a pin array carrier assembly comprising a pin array top surface at a test site;

adjusting said pin array carrier assembly to contact said pin array top surface with probes of a probe card;

sending first signals to each of said probes;

receiving second signals through said pin array top surface;

decoding said second signals;

identifying an X-coordinate, Y-coordinate, and THETA-coordinate of each of said probes through said decoded second signals.

26. The method of claim 25 wherein said pin array comprising a plurality of pins.

27. The method of claim 25 further comprising a step of adjusting said THETA-coordinate of said probe card by reference to a known standard.

28. A method of manufacture for a semiconductor integrated circuit comprising the steps of:

providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being untested;

separating each of said semiconductor integrated circuits from said fabricated wafer; and

probing each of said semiconductor integrated circuits, said semiconductor integrated circuits being unpackaged.

29. A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of:

providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said fabricated wafer being substantially free from electrical tests; and

entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.