VCSEL having a self-aligned heat sink and method of making
First Claim
1. A method for making a VCSEL with a self-aligned integrated heat sink comprising the steps of:
- providing a substrate having a surface with a first stack of distributed Bragg reflectors, a first cladding region, an active region, a second cladding region, a second stack of distributed Bragg reflectors, and a contact region;
forming a first dielectric layer on said contact region;
forming a mesa with a surface and a trench, wherein said trench extends from said first dielectric layer into a portion of said second stack of distributed Bragg reflectors, and wherein said trench is adjacent to a portion of said mesa;
forming a second dielectric layer overlying said substrate so that a portion of said second dielectric layer covers a portion of said trench while exposing a portion of said contact region on said mesa;
forming a conductive layer on said second dielectric layer and on said mesa;
forming a seed layer on said conductive layer;
forming a dielectric area on said seed layer above said surface of said mesa; and
plating a metal selectively on said seed layer generating a layer on said seed layer for removal of heat, thereby generating an integrated heat sink.
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Accused Products
Abstract
A substrate (102) having a surface (103) with a first stack of distributed Bragg reflectors (106), a first cladding region (107), an active region (108), a second cladding region (109), a second stack of distributed Bragg reflectors (110), and a contact region (111) is provided. A mesa (131) with a surface (133) and a trench (136) is formed. A first dielectric layer (122) is formed overlying substrate (102) and covering a portion of trench (136). A second dielectric layer (128) is formed on surface (133) of mesa (131). A seed layer (126) having a pattern is formed, with the pattern of seed layer (126) having an opening on a portion of second dielectric layer (128) of mesa (131). A metal is selectively plated on seed layer (126), thereby generating a layer (204) on seed layer (126) for removal of heat from VCSEL (101).
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Citations
17 Claims
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1. A method for making a VCSEL with a self-aligned integrated heat sink comprising the steps of:
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providing a substrate having a surface with a first stack of distributed Bragg reflectors, a first cladding region, an active region, a second cladding region, a second stack of distributed Bragg reflectors, and a contact region; forming a first dielectric layer on said contact region; forming a mesa with a surface and a trench, wherein said trench extends from said first dielectric layer into a portion of said second stack of distributed Bragg reflectors, and wherein said trench is adjacent to a portion of said mesa; forming a second dielectric layer overlying said substrate so that a portion of said second dielectric layer covers a portion of said trench while exposing a portion of said contact region on said mesa; forming a conductive layer on said second dielectric layer and on said mesa; forming a seed layer on said conductive layer; forming a dielectric area on said seed layer above said surface of said mesa; and plating a metal selectively on said seed layer generating a layer on said seed layer for removal of heat, thereby generating an integrated heat sink. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for making a VCSEL having a heat sink comprising the steps of:
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forming a partially fabricated VCSEL having a mesa with a surface and a trench adjacent to the mesa, the surface of the mesa being centrally located; forming a seed layer in the trench and on the mesa; forming a dielectric area on the surface of the mesa; and plating a second metal selectively on the seed layer, thereby generating a VCSEL. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for making a VCSEL having auto-aligned heat sink comprising the steps of:
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providing a substrate having a surface with a first stack of distributed Bragg reflectors, a first cladding region, an active region, a second cladding region, a second stack of distributed Bragg reflectors, and a contact region; forming a layer on the contact region; forming a masking layer having a ring shaped pattern on the layer, the ring shaped pattern of the masking layer exposes portions of the layer, while covering other portions of the layer; etching the exposed portions of the layer, thereby removing exposed portions of the layer and exposing portions of the contact region; etching the exposed portions of the contact region and into a portion of the second stack of distributed Bragg reflectors to form a mesa, thereby forming a trench adjacent to the mesa; forming a dielectric layer overlying portions of the contact region and covering a portion of the trench; forming a seed layer overlying the substrate; forming a dielectric area on the seed layer; and plating a second metal selectively on the seed layer, thereby selectively plating the second metal on the seed layer and exposing a portion of the dielectric area. - View Dependent Claims (16)
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17. A method for sizing an emission hole of a VCSEL comprising the steps of:
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providing a substrate having a surface with a first stack of distributed Bragg reflectors, a first cladding region, an active region, a second cladding region, a second stack of distributed Bragg reflectors, and a contact region; forming a first dielectric layer on said contact region; forming a mesa with a surface and a trench, wherein said trench extends from said first dielectric layer into a portion of said second stack of distributed Bragg reflectors, and wherein said trench is adjacent to a portion of said mesa; forming a second dielectric layer overlying said substrate so that a portion of said second dielectric layer covers a portion of said trench while exposing a portion of said contact region on said mesa; forming a conductive layer on said second dielectric layer and on said mesa; forming a seed layer on said conductive layer; forming a dielectric area on said seed layer above said surface of said mesa; and plating a metal selectively on said seed layer generating a layer on said seed layer, as well as generating portions that encroach on the dielectric area, thereby sizing an emission hole of the VCSEL.
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Specification