Magnetic spin injected field effect transistor and method of operation
First Claim
1. A magnetic spin injected transistor device comprising:
- first and second separated high conductance regions;
a first ferromagnetic layer having a first coercivity, and electrically coupled to said first high conductance region;
a second ferromagnetic layer having a second coercivity smaller than said first coercivity, and electrically coupled to said second high conductance region; and
a gate situated between said high conductance regions.
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Accused Products
Abstract
A new hybrid magnetic spin injected-FET structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid FET uses ferromagnetic materials for the source and drain, and like a conventional FET, has two operating states determined by a gate voltage, "off" and "on". The ferromagnetic layers of the hybrid FET are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the "on" state the spin injected FET has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic source and drain. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the drain to be parallel or antiparallel with that of the source, thus changing the resistance of the device to a current of spin polarized electrons injected into the source and flowing to the drain through the channel under the gate. The new FET can be used as a memory cell because the drain magnetization is non-volatile, and can represent a binary data value to be stored in the cell. A conductive write line can be used for inductively coupling an input magnetic field (representing a data value to be stored in the device) with the drain magnetization to alter the orientation state of the latter. An array of spin injected FETs can be coupled together in an array to form a new hybrid FET memory array. The new FET can also be used as a logic gate that stores the result of a boolean function. A magnetic field generated by the combined current of one or more input data signals is coupled to the spin injected FET. Depending on the particular function to be implemented, the ferromagnetic drain magnetization can be configured to change or retain its orientation based on particular predefined combinations of input data signals.
329 Citations
59 Claims
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1. A magnetic spin injected transistor device comprising:
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first and second separated high conductance regions; a first ferromagnetic layer having a first coercivity, and electrically coupled to said first high conductance region; a second ferromagnetic layer having a second coercivity smaller than said first coercivity, and electrically coupled to said second high conductance region; and a gate situated between said high conductance regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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19. A magnetic spin injected transistor device comprising:
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a first ferromagnetic layer for generating spin polarized electrons and having a first magnetization orientation; a first high conductance region coupled to the first ferromagnetic layer; a second ferromagnetic layer having a second magnetization orientation; a second high conductance region coupled to the second ferromagnetic layer; a gate situated between said first and second high conductance regions for controlling electrical conductance of a channel region connecting the first and second high conductance regions in response to a control signal; wherein a spin polarized current comprised of spin polarized charge carriers flows from the first ferromagnetic layer to the second ferromagnetic layer when the channel is controlled to have a high electrical conductance; and wherein the spin injected charge carrier current has a first value when the first and second magnetization orientations are the same, and has a second, different value when the first and second magnetization orientations are different.
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38. A logic device for implementing a logic function relating a combination of one or more input signals to an output signal comprising:
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a first ferromagnetic layer having a first magnetization orientation, for generating spin polarized electrons; a first high conductance region coupled to the first ferromagnetic layer; a second ferromagnetic layer having a second magnetization orientation; a second high conductance region coupled to the second ferromagnetic layer; a gate situated between said first and second high conductance regions for controlling electrical conductance of a channel region connecting the first and second high conductance regions in response to a control signal; a wire for inductively coupling said second ferromagnetic layer with a magnetic field generated by the combination of one or more input data signals on said wire, the input data signals having either a first or second current value, and whereby the second ferromagnetic layer magnetization orientation is alterable by magnetic fields corresponding to combinations of said input data signals related to said logic function; said output signal corresponding to a spin polarized current comprised of spin polarized charge carriers, and having a first value when the first and second magnetization orientations are the same, and having a second, different value when the first and second magnetization orientations are different. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A memory cell for storing a data state corresponding to one of a first and a second logical data value, said memory cell comprising:
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a first ferromagnetic layer having a first magnetization orientation; a first high conductance region coupled to the first ferromagnetic layer; a second ferromagnetic layer having a second alterable magnetization orientation; a second high conductance region coupled to the second ferromagnetic layer; a gate situated between said first and second high conductance regions for controlling electrical conductance of a channel region connecting the first and second high conductance regions in response to a cell select signal; and wherein said memory element stores the first logical value when the first and second magnetization orientations are aligned, and the second logical value when the first and second magnetization orientations are opposite. - View Dependent Claims (49, 50, 51, 52)
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53. A method of operating a hybrid magnetic spin injected-field effect transistor device comprising the steps of:
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providing a current of spin polarized charge carriers to flow from a first ferromagnetic layer to a second ferromagnetic layer; controlling the flow of spin polarized charge carriers between the two layers by applying a control signal to a gate of the field effect transistor having a channel interposed between the two layers; and controlling the quantity of spin polarized current flowing in the device by aligning a second magnetization orientation state of the second ferromagnetic layer relative to a first magnetization orientation state of the first ferromagnetic layer; whereby when said control signal is applied, a relatively high amount of spin polarized current flows in said device when the magnetization orientation states of the two ferromagnetic layers are the same, and a relatively small amount of spin polarized current flows in said device when the magnetization orientation states of the two ferromagnetic layers are opposite to each other. - View Dependent Claims (54, 55, 56, 57, 58, 59)
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Specification