CMOS gate stack

• US 5,654,570 A
• Filed: 04/19/1995
• Issued: 08/05/1997
• Est. Priority Date: 04/19/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Agnello, Paul David
• Primary Examiner(s): Whitehead, Carl W.
• Application Number:
  US08/425,945
• Time in Patent Office: 839 Days
• Field of Search: 257/204, 257/213, 257/249, 257/250, 257/262, 257/263, 257/274, 257/288, 257/331, 257/332, 257/338, 257/368, 257/369, 257/412
• US Class Current: 257/338
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916

Abstract

A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain junction, and is preferably of greater width than the gate.

Claims

1. A CMOS gate stack comprising a semiconductor substrate;

device isolation regions on or in said substrate or both on and in said substrate;

gate isolation layer over active regions of said substrate as defined by said device isolation regions;

polysilicon gate located above said gate isolation layer;

self-aligned metallic gate conductor above said polysilicon gate wherein said metallic gate conductor is wider than said polysilicon gate.

2. The gate stack of claim 1 wherein said substrate is silicon.

3. The gate stack of claim 1 wherein said device isolation regions is silicon dioxide.

4. The gate stack of claim 1 which further comprises a cap dielectric.