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CMOS gate stack

  • US 5,654,570 A
  • Filed: 04/19/1995
  • Issued: 08/05/1997
  • Est. Priority Date: 04/19/1995
  • Status: Expired due to Fees
First Claim
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1. A CMOS gate stack comprising a semiconductor substrate;

  • device isolation regions on or in said substrate or both on and in said substrate;

    gate isolation layer over active regions of said substrate as defined by said device isolation regions;

    polysilicon gate located above said gate isolation layer;

    self-aligned metallic gate conductor above said polysilicon gate wherein said metallic gate conductor is wider than said polysilicon gate.

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