Electrostatic discharge protection device for integrated circuit

• US 5,654,574 A
• Filed: 06/06/1995
• Issued: 08/05/1997
• Est. Priority Date: 10/19/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Hille, Peter, Wrathall, Robert G.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/486,280
• Time in Patent Office: 791 Days
• Field of Search: 257/173, 257/327, 257/355, 257/357, 257/360, 361/56, 361/91, 361/111, 327/313
• US Class Current: 257/355
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/025 Current limitation using field effect transistors
• CPC Class Codes: H02H 9/042 comprising means to limit the absorbed power or indicate damaged over-voltage protection device
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

An electrostatic discharge (ESD) device includes a pair of depletion mode MOSFETs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs, and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike (in an automobile, sometimes referred to as a "load dump"), while the second MOSFET saturates, limiting the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.

Claims

1. An ESD protection arrangement comprising an IC device and first and second ESD protection circuits, each of said ESD protection circuits comprising two depletion mode MOSFETs connected in series drain-to-drain between an input terminal and an output terminal of said circuit, each of said MOSFETs having a gate, a body and a source shorted together, a common node between said MOSFETs being connected to ground through a first diode a source terminal of one of said MOSFETs being connected through a series resistor to said output terminal and to a cathode of a second diode, an anode of said second diode being connected to ground, the output terminal of said first ESD protection circuit being coupled to internal circuitry of the IC device, the output terminal of said second ESD protection circuit being coupled to a power supply rail of said IC device.

6. The ESD protection arrangement of claims 1 wherein the first diode has a breakdown voltage comparable to a breakdown voltage of each of said MOSFETs.

2. An ESD protection arrangement comprising an IC device and first and second ESD protection circuits the first ESD protection circuit comprising first and second depletion mode MOSFETs connected in series drain-to-drain between an input terminal and an output terminal of the first ESD protection circuit, each of said first and second MOSFETs having a gate, a body and a source shorted together, a common node between said first and second MOSFETs being connected to ground through a first diode a source terminal of said second MOSFET being connected through a series resistor to the output terminal of the first ESD protection circuit the output terminal of said first ESD protection circuit being coupled to internal circuitry of the IC device, said second ESD protection circuit comprising a third depletion mode MOSFET connected between an input terminal and an output terminal of said second ESD protection circuit, said third MOSFET having a gate, a body and a source shorted together, a drain of said third MOSFET being connected to ground through a second diode a source terminal of said third MOSFET being connected to an output terminal of said second ESD protection circuit, the output terminal of said second ESD protection circuit being coupled to a power supply rail of said IC device.

7. The ESD protection arrangement of claim 2 wherein the first diode has a breakdown voltage comparable to a breakdown voltage of each of said first and second MOSFETs of the first ESD protection circuit and the second diode has a breakdown voltage comparable to a breakdown voltage of the third MOSFET.

8. The ESD protection arrangement of claim 2 wherein the second ESD protection circuit further comprises a third diode, a cathode of the third diode being connected to the source terminal of the third MOSFET, and an anode of the third diode being connected to ground.

9. The ESD protection arrangement of claims 8 further comprising a CMOS input buffer, the CMOS input buffer being connected between the output terminal of the first ESD protection circuit and the internal circuitry of the IC device, the CMOS input buffer containing a PMOS transistor and an NMOS transistor, the PMOS transistor and the NMOS transistor being connected in series between the power supply rail and ground, respective gate terminals of the PMOS transistor and the NMOS transistor being connected to the output terminal of the first ESD protection circuit, a common drain node of the PMOS transistor and the NMOS transistor being connected to the internal circuitry of the IC device.

10. The ESD protection arrangement of claim 2 wherein the first ESD protection circuit further comprises a third diode, a cathode of the third diode being connected to the output terminal of the first ESD protection circuit, and an anode of the third diode being connected to ground.

14. The ESD protection arrangement of claim 2 wherein said first MOSFET in said first ESD protection circuit is connected through a second series resistor to the input terminal of the first ESD protection circuit and through said second series resistor and a series combination of fifth and sixth diodes to ground, said fifth and sixth diodes being connected with opposed polarities in said series combination.

3. An ESD protection circuit for protecting internal circuitry of an IC device, said circuit comprising an input terminal, an output terminal to be connected to the IC device, a depletion mode MOSFET, said MOSFET having a gate, a body and a source shorted together, and a drain connected to ground through a first diode a source terminal of said MOSFET being connected to the output terminal of said ESD protection circuit and through a series resistor to a cathode of a second diode, an anode of said second diode being connected to ground.

4. The ESD protection circuit of claim 3 wherein said first and second MOSFETs are formed in a tub formed in an N-type epitaxial layer.

5. The ESD protection circuit of claim 4 wherein said MOSFETs are separated by and surrounded by a heavily-doped diffusion of N-type semiconductor material which extends between a surface of said N-type epitaxial layer and an N-type buried layer.

11. The ESD protection circuit of claim 3 wherein the first diode has a breakdown voltage comparable to a breakdown voltage of said MOSFET.

13. The ESD protection arrangement of claim 11 wherein the first diode has a breakdown voltage comparable to a breakdown voltage of each of said MOSFETs.

12. An ESD protection arrangement comprising an IC device and an ESD protection circuit wherein the ESD protection circuit comprises two depletion mode N-channel MOSFETs connected in series drain-to-drain between a tri-state buffer and an input/output terminal of the IC device, each of said MOSFETs having a gate, a body and a source shorted together, a common node between said MOSFETs being connected to ground through a first diode, a source terminal of one of said MOSFETs being connected through a series resistor to the tri-state buffer and to a cathode of a second diode, an anode of the second diode being connected to ground.

15. An ESD protection circuit comprising an input terminal, an output terminal, a depletion mode MOSFET connected between said input terminal and said output terminal, the source, body and gate of said MOSFET being shorted together and connected to said output terminal, a first diode having a cathode connected to a drain of said MOSFET and an anode connected to ground, and a second diode having a cathode connected to the output terminal and an anode connected to ground.

16. The circuit of claim 15 wherein a breakdown voltage of the first diode is greater than a breakdown voltage of the second diode.

17. The circuit of claim 15 wherein the first diode has a breakdown voltage of approximately 70V.

18. The circuit of claim 15 wherein the second diode has a breakdown voltage in the range of from 20V to 25V.

19. The circuit of claim 15 wherein the output terminal is connected to an IC device and the second diode has a breakdown voltage which is greater than a maximum allowed signal input voltage to the IC device.

20. The circuit of claim 15 wherein the output terminal is connected to an IC device containing a logic MOSFET and the second diode has a breakdown voltage which is approximately equal to 50% of a gate oxide rupture voltage of the logic MOSFET.

21. The circuit of claim 15 wherein the depletion mode MOSFET is double-diffused.

22. The circuit of claim 15 wherein the MOSFET has a resistance of between 20 and 2000 ohms.

23. The circuit of claim 15 further comprising a series resistance connected between the output terminal and the source/body terminal of the depletion mode MOSFET.

24. The circuit of claim 23 wherein the series resistor has a resistance in the range of from 20 to 2000 ohms.

25. The circuit of claim 15 wherein the circuit is included in an IC.

26. The circuit of claim 15 wherein the circuit is included in an IC formed using a junction isolated process on an N-type epitaxial layer grown on a P-type substrate.