Multi-function network

• US 5,654,695 A
• Filed: 02/23/1996
• Issued: 08/05/1997
• Est. Priority Date: 02/22/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Heidelberger, Philip, Franaszek, Peter Anthony, Rathi, Bharat Deep, Varma, Anujan Mangala, Olnowich, Howard Thomas, Barker, Thomas Norman
• Primary Examiner(s): Holloway, III, Edwin C.
• Application Number:
  US08/606,232
• Time in Patent Office: 529 Days
• Field of Search: 340/825.01, 340/825.03, 340/826, 340/827, 340/825.79, 340/825.8, 340/825.85, 340/825.86, 340/825.87, 370/16, 370/54, 370/60.1, 370/58.1, 395/200.02, 395/200.15, 395/182.02, 395/311
• US Class Current: 340/2.23
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.

Claims

1. A multi-stage bufferless switching network, the network comprising:

a plurality of bufferless switching apparatuses cascaded into stages, each said switching apparatus including a plurality of switch inputs and a plurality of switch outputs, each of said switch outputs coupled to a switch input of another of said switching apparatuses, the switch outputs of last stage switching apparatuses each coupled to a switch input of a first stage switching apparatus through one of a plurality of nodes, the switch outputs of last stage switching apparatuses comprising network output ports and the switch inputs of first stage switching apparatuses comprising network input ports;

the switching apparatuses each including;

means for establishing a plurality of direct connections, a direct connection connecting any one of the network input ports to any one of the network output ports, in response to connection requests received at a plurality of the network input ports, for transmitting data from said plurality of the network input ports to a plurality of the network output ports, the direct connection comprising one of a plurality of pathways connectable from said any one of the network input ports to said any one of the network output ports; and

detecting means coupled to each switch output for detecting a blocked switch output in the pathway of the direct connection; and

each of the nodes including;

rearrangeability means coupled to a connected network input port for sending a connection request to the connected network input port for an alternate direct connection between said any one of the network input ports and said any one of the network output ports in response to said detecting means detecting the blocked switch output.

2. The network according to claim 1, wherein each of said nodes further include one or more network devices, thereby allowing each of the network devices to transmit data to any other of the network devices via one network input port and one network output port.

3. The network according to claim 1, wherein the rearrangeability means includes:

address register that stores at least part of an address of a targeted node;

multiplexor means, operably coupled to the address register, for providing an alternate path selection based on the at least part of the address of the targeted node or based on an updated address;

a first counter that provides a control signal for determining whether the multiplexor means will provide the alternate path selection based on the at least part of the address of the targeted node or based on an updated address; and

a second counter operably coupled to the multiplexor means, wherein the second counter provides the updated address.

4. The network according to claim 1 wherein said means for establishing a plurality of direct connections establishes said direct connections simultaneously and asynchronously in relation to a plurality of connection requests received separately at a plurality of the network input ports.