Semiconductor memory device with reduced read time and power consumption

• US 5,654,912 A
• Filed: 12/07/1995
• Issued: 08/05/1997
• Est. Priority Date: 12/07/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hasegawa, Takehiro, Oowaki, Yukihito, Kuyama, Hitoshi
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/568,500
• Time in Patent Office: 607 Days
• Field of Search: 365/149, 365/189.12, 365/205, 365/190, 365/230.03
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4045 using a plurality of serially connected access transistors, each having a storage capacitor
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

Claims

1. A semiconductor memory device comprising:

at least one memory array which has memory cells, word lines driven by a row decoder, and bit lines for reading data from said memory cells, said memory array further having a plurality of memory cell units which have a plurality of said memory cells connected together in series;

a plurality of sense amplifiers provided to read out data from said memory cell units in said memory array, each of said plurality of sense amplifiers being formed into subsets of sense amplifier blocks with all of the sense amplifiers forming a given sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node, with at least said first data node of each of said plurality of sense amplifier blocks being selectively connected to at least one of said bit lines in said memory array when data is to be read or written;

a plurality of register blocks corresponding to said plurality of sense amplifier blocks, each of said plurality of register blocks including a plurality of registers receiving and storing data amplified by said plurality of sense amplifiers; and

a control circuit for independently controlling each of said plurality of Sense amplifier blocks and said plurality of register blocks to independently read out data from each of said plurality of register blocks.

2. A semiconductor memory device according to claim 1, wherein each of said plurality of registers temporarily stores data read out from said memory units, and

said control circuit controls the reading out of data from said plurality of registers to an external device without any need to first return the data to said memory cell units.

3. A semiconductor memory device according to claim 1, further comprising:

an input address executing device which selects a register in said plurality of register blocks in addition to responding to a row address and a column address.

4. A semiconductor memory device according to claim 3, wherein

each of said plurality of registers temporarily stores data read out from said memory cell units, and

said control unit controls the reading out of data from said plurality of registers to an external device without any need to first return the data to said memory cell units.

5. A device according to claim 1, wherein said plurality of registers in a register block are all connected to one of said first data node and said second data node of each of said plurality of sense amplifiers in the corresponding sense amplifier block.

6. A semiconductor memory device according to claim 1, further comprising a switching device which selectively connects said bit lines to one of said first data node and said second data node of each of said plurality of sense amplifiers.

7. A semiconductor memory device according to claim 1, wherein said plurality of memory cells and said plurality of registers respectively include dynamic memory cells.

8. A semiconductor memory device according to claim 1, wherein said plurality of memory cells are selected from the group consisting of NOR, NAND, and AND cells.

9. A semiconductor memory device comprising:

at least one memory array which has memory cells, word lines being driven by a row decoder and data from for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;

a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node;

a plurality of switching array blocks corresponding to said plurality of sense amplifier blocks, said plurality of switching array blocks each having a plurality of switching elements which connect a pair of bit lines to said first node and to said second node of each of said plurality of sense amplifiers when data is to be read or written; and

a control circuit for independently controlling each of said plurality of sense amplifier blocks and said corresponding plurality of said switching blocks to independently read out data from said memory cells in said memory array.

10. A semiconductor memory device comprising:

at least one memory array which has memory cells, word lines being driven by a row decoder and bit lines for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;

a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node, with at least said first data node of each of said plurality of sense amplifier blocks being selectively connected to at least one of said bit lines in said memory array when data is to be read or written;

a plurality of register blocks corresponding to said plurality of sense amplifier blocks, each of said plurality of register blocks including a plurality of registers receiving and storing data amplified by said plurality of sense amplifiers; and

a control circuit for independently controlling each of said plurality of sense amplifier blocks and said plurality of register blocks to independently read out data from each of said plurality of register blocks.

11. A semiconductor memory device comprising:

at least one memory array which has memory cells, word lines being driven by a row decoder and bit lines for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;

a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node;

a plurality of register blocks corresponding to said plurality of sense amplifier blocks, each of said plurality of register blocks including a plurality of registers receiving and storing data amplified by said plurality of sense amplifiers;

a plurality of switching array blocks corresponding to said plurality of sense amplifier blocks, said plurality of switching array blocks each having a plurality of switching elements which selectively connect a pair of bit lines to said first node and said second node of each of said plurality of said sense amplifiers when data is read or written; and

a control circuit for independently controlling each of said plurality of sense amplifier blocks, said plurality of switching array blocks, and said plurality of register blocks so as to independently read out data from each of said plurality of register blocks.