Semiconductor memory device having low power self refresh and burn-in functions

• US 5,654,930 A
• Filed: 08/30/1996
• Issued: 08/05/1997
• Est. Priority Date: 06/04/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Seung-Moon, Haq, Ejaz Ul
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/705,040
• Time in Patent Office: 340 Days
• Field of Search: 365/222, 365/230.06, 365/236, 365/239, 365/240
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells arranged in an array of rows and columns;

a word line arranged in each row, each word line selecting one of said rows of said plurality of memory cells in response to an input of a row address;

a bit line arranged in each column, each bit line selecting one of said columns of said plurality of memory cells in response to an input of a column address;

a decoder disposed in close proximity to said array for selecting one of said word lines in response to an input of said row address;

a counter disposed in a peripheral region further from said array than said decoder, said counter generating at least a first row address signal that causes selection of a first word line by said decoder; and

a controller for executing a selection operation of another word line based upon said first row address signal so that charging of a row address signal line disposed between said decoder and said counter is not required during said selection operation.

2. The semiconductor memory device as claimed in claim 1, wherein said another word line is an adjacent word line.

3. A semiconductor memory device according to claim 1 wherein a plurality of word lines are selected during a respective plurality of selection operations without charging of said row address signal line.

4. A semiconductor memory device according to claim 1 wherein said selection operation occurs during a self-refresh operation.

5. A semiconductor memory device according to claim 4 wherein a plurality of word lines are selected during a respective plurality of selection operations without charging of said row address signal line.

6. A semiconductor memory device comprising:

a plurality of memory cells arranged in an array of rows and columns;

a word line arranged in each row, each word line selecting one of said rows of said plurality of memory cells in response to an input of a row address;

a bit line arranged in each column, each bit line selecting one of said columns of said plurality of memory cells in response to an input of a column address;

a decoder disposed in close proximity to said array for selecting one of said bit lines in response to an input of said column address;

a counter disposed in a peripheral region further from said array than said decoder, said counter generating at least a first column address signal that causes selection of a first bit line by said decoder; and

a controller for a executing selection operation of another bit line based upon said first column address signal so that charging of a column address signal line disposed between said decoder and said counter is not required during said selection operation.

7. The semiconductor memory device as claimed in claim 6, wherein said another bit line is an adjacent bit line.

8. A semiconductor memory device according to claim 6 wherein a plurality of bit lines are selected during a respective plurality of selection operations without charging of said column address signal line.

9. A semiconductor memory device according to claim 6 wherein said selection operation occurs during a self-refresh operation.

10. A semiconductor memory device according to claim 9 wherein a plurality of bit lines are selected during a respective plurality of selection operations without charging of said column address signal line.

11. A semiconductor memory device comprising:

a first word line connected to a first plurality of memory cells;

a second word line connected to a second plurality of memory cells that is adjacent to said first plurality of memory cells;

a first word line driver for driving said first word line in response to a first combination input of a row address;

a second word line driver for driving said second word line; and

a register arranged between said first and second word line drivers for selecting said second word line driver in response to a given control signal, after selecting said first word line driver.

12. The semiconductor memory device as claimed in claim 11, wherein said control signal is an oscillating signal which is generated from an oscillator during a self-refresh operation.

13. The semiconductor memory device as claimed in claim 11, wherein said control signal is a burn-in signal which is enabled during a burn-in operation.

14. A semiconductor memory device comprising:

memory cell array having a plurality of memory cells in rows and columns;

a first word line driver for selecting a first word line connected to a row of first memory cells arranged in the row direction;

a second word line driver for selecting a second word line connected to a row of second memory cells arranged in the row direction;

a first row decoder for driving said first word line driver in response to a first combination input of a row address;

a second row decoder for driving said second word line driver; and

a register for driving said second word line driver using an output of said first row decoder in response to a given control signal, said register having an input terminal connected to an output terminal of said first row decoder and an output terminal connected to an input terminal of said second row decoder.

15. The semiconductor memory device as claimed in claim 14, wherein said control signal is an oscillating signal which is generated from an oscillator during a self-refresh operation.

16. The semiconductor memory device as claimed in claim 14, wherein said control signal is a burn-in signal which is enabled during a burn-in operation.