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Semiconductor memory device having low power self refresh and burn-in functions

  • US 5,654,930 A
  • Filed: 08/30/1996
  • Issued: 08/05/1997
  • Est. Priority Date: 06/04/1994
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a plurality of memory cells arranged in an array of rows and columns;

    a word line arranged in each row, each word line selecting one of said rows of said plurality of memory cells in response to an input of a row address;

    a bit line arranged in each column, each bit line selecting one of said columns of said plurality of memory cells in response to an input of a column address;

    a decoder disposed in close proximity to said array for selecting one of said word lines in response to an input of said row address;

    a counter disposed in a peripheral region further from said array than said decoder, said counter generating at least a first row address signal that causes selection of a first word line by said decoder; and

    a controller for executing a selection operation of another word line based upon said first row address signal so that charging of a row address signal line disposed between said decoder and said counter is not required during said selection operation.

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