Method and apparatus for testing a sytem component with test checkpointing

• US 5,655,072 A
• Filed: 04/12/1996
• Issued: 08/05/1997
• Est. Priority Date: 04/12/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Information Systems America Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Wolff, Robert M.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/631,523
• Time in Patent Office: 480 Days
• Field of Search: 395/183.01, 395/183.06, 395/183.2, 395/700, 364/DIG. 1, 364/DIG. 2, 364/267, 364/265, 364/262.4, 371/3, 371/46, 371/69.1, 371/183.12, 371/183.07, 371/183.22
• US Class Current: 714/25
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

An apparatus and method for testing the installation and functioning of a component of computer system has a test engine which causes the identity of a test to be performed to be stored in a nonvolatile memory before being performed. The test is announced to the installer and then ran. This procedure is performed for a sequence of tests. In the event of a crash during testing, the step-by-step sequencing of the tests and the storage of the test identifies step-by-step in the nonvolatile memory simplifies identification of the test that caused the crash for the installer.

Claims

1. A method of testing a component of a computer system, the computer system having a nonvolatile memory, comprising the steps of:

a) informing a user of a test to be performed on the component;

b) storing information identifying the test in the nonvolatile memory;

c) performing the test on the component;

d) if the test was successfully completed, repeating steps a-c for another test until all tests for the component are successfully completed; and

e) if any test is not successfully completed, retrieving the information identifying that test from the nonvolatile memory and informing the user of the identity of that test.

2. The method of claim 1, wherein the information identifying the test includes solution information identifying to the user possible solutions to causes for any test not completing when that test does not successfully complete.

3. The method of claim 2, wherein the information identifying the test further includes description information that describes the test to a user.

4. The method of claim 1, wherein the tests are performed in a sequence of tests, the method further comprising continuing the sequence of tests following the test that did not successfully complete after the step of informing the user of the identity of that test that did not successfully complete.

5. The method of claim 2, wherein the tests are performed in a sequence of tests, the method further comprising the steps of halting the sequence of tests after a test is not successfully completed, clearing the information identifying that test from the nonvolatile memory, and restarting the sequence of tests from a first one of the tests in the sequence.

6. The method of claim 2, wherein the tests are performed in a sequence of tests, the method further comprising the steps of halting the sequence of tests after a test is not successfully completed, clearing the information identifying that test from the nonvolatile memory, and restarting the sequence of tests starting from the test that did not successfully complete.

7. A computer-readable medium having stored thereon instructions which, when executed by a processor, cause said processor to perform the steps of:

a) informing a user of a test to be performed on a component coupled to a computer system;

b) storing information identifying the test in a nonvolatile memory of the computer system;

c) controlling performing of the test on the component;

d) if the test was successfully completed, repeating steps a-c for another test until all tests for the component are successfully completed; and

e) if any test is not successfully completed, retrieving the information identifying that test from the nonvolatile memory and informing the user of the identity of that test.

8. The medium of claim 7, wherein the information identifying the test includes solution information identifying to the user possible solutions to causes for any test not completing when that test does not successfully complete.

9. The medium of claim 8, wherein the information identifying the test further includes description information that describes the test to a user.

10. The medium of claim 7, wherein the tests are performed in a sequence of tests, the medium further having instructions which cause said processor to continue the sequence of tests following the any test did not successfully complete after the step of informing the user of the identity of that test that did not successfully complete.

11. The medium of claim 8, wherein the tests are performed in a sequence of tests, the medium further having instructions which cause said processor to halt the sequence of tests after a test is not successfully completed, clear the information identifying that test from the nonvolatile memory, and restart the sequence of tests from a first one of the tests in the sequence.

12. The medium of claim 8, wherein the tests are performed in a sequence of tests, the medium further having instructions which cause said processor to halt the sequence of tests after a test is not successfully completed, clear the information identifying that test from the nonvolatile memory, and restart the sequence of tests starting from the test that did not successfully complete.

13. A computer system comprising:

a central processing unit;

a nonvolatile memory coupled to the central processing unit;

a video board coupled to the central processing unit; and

a test engine used by the central processing unit to a) inform a user of a test to be performed on the video board, b) store information identifying the test in the nonvolatile memory, c) perform the test on the video board, if the test was successfully completed, repeating a)-c) for another test until all tests for the component are successfully completed, and if any test is not successfully completed, retrieve the information identifying that test from the nonvolatile memory and informing the user of the identity of that test.

14. The computer system of claim 13, further comprising a video monitor coupled to the video board, the video monitor displaying the information identifying the test.

15. The computer system of claim 13, wherein the nonvolatile memory is a memory storage disk.

16. The computer system of claim 13, wherein the nonvolatile memory is an erasable programmable read only memory.

17. The computer system of claim 13, wherein the test engine includes means for providing solution information to the user which identifies possible solutions to causes for that test not completing when that test does not successfully complete.

18. The computer system of claim 13, wherein the test engine includes means for describing the test that will be performed to a user.

19. The computer system of claim 13, wherein the test engine includes means for causing the tests to be performed by the central processing unit in a sequence of tests, the test engine having instructions which cause said processor to continue the sequence of tests following the test that did not successfully complete after the step of informing the user of the identity of that test that did not successfully complete.

20. The computer system of claim 13, wherein the test engine includes means for causing the tests to be performed by the central processing unit in a sequence of tests, the test engine having instructions which cause said processor to halt the sequence of tests after a test is not successfully completed, clear the information identifying that test from the nonvolatile memory, and restart the sequence of tests from a first one of the tests in the sequence.

21. The computer system of claim 13, wherein the test engine includes means for causing the tests to be performed by the central processing unit in a sequence of tests, the test engine having instructions which cause said processor to halt the sequence of tests after a test is not successfully completed, clear the information identifying that test from the nonvolatile memory, and restart the sequence of tests starting from the test that did not successfully complete.