Computer system for transferring information streams in a plurality of formats without control information regarding the information streams

• US 5,655,091 A
• Filed: 04/05/1995
• Issued: 08/05/1997
• Est. Priority Date: 01/30/1992
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Roskowski, Steven G., Drako, Dean M.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): DINH, DUNG C
• Application Number:
  US08/417,400
• Time in Patent Office: 853 Days
• Field of Search: 395/306, 395/309, 395/853, 395/849, 395/285, 395/286
• US Class Current: 710/106
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

An arrangement for transmitting information from a first component of a computer system to a second component of the computer system including a source channel associated with the first component of the computer system; a destination channel associated with the second component of the computer system; apparatus for interconnecting the source and the destination channels; the source channel including apparatus for creating a stream of information in a prescribed format, apparatus for designating a destination channel as an address for the stream of information, and apparatus for transferring the stream of information to the apparatus for interconnecting the source and the destination channels; and the destination channel including apparatus for receiving a stream of information in the prescribed format from the apparatus for interconnecting the source and the destination channels, apparatus for receiving control signals apart from the stream of information, and apparatus for controlling the use of the stream of information in response to the control signals.

Claims

1. A source channel operative to receive information from a first component of a computer system and provide an information stream to an interconnect which is for coupling to a destination channel that controls transfer of the information stream to a second component, the source channel comprising:

first circuitry coupled to the first component, said first circuitry creating the information stream in a selected one of a of prescribed formats using information received from the first component;

second circuitry coupled to said interconnect, said second circuitry designating said destination channel as an address for the information stream; and

third circuitry coupled to the interconnect and transferring the information stream to the interconnect, wherein the information stream includes no control information regarding the information stream.

2. A source channel as claimed in claim 1, wherein the first circuitry for creating an information stream in a selected one of a plurality of prescribed formats comprises:

fourth circuitry coupled to the first component, said fourth circuitry storing information to be transferred into the information stream;

fifth circuitry coupled to the fourth circuitry, said fifth circuitry selecting a starting point in the information stored by the fourth circuitry;

sixth circuitry coupled to the fourth circuitry, said sixth circuitry selecting an ending point in the information stored by the fourth circuitry; and

seventh circuitry separating information from the starting point to the ending point for the information stream.

3. The source channel as claimed in claim 2 in which the fourth circuitry comprises a first register, the fifth circuitry comprises a second register, the sixth circuitry comprises a third register, and the seventh circuitry comprises a plurality of registers for storing information regarding the width of rows and the number of rows of information to be selected, and further comprising eighth circuitry decrementing the values stored in the plurality of registers as information is placed in the information stream.

4. The source channel as claimed in claim 2 further comprising translating circuitry coupled to the fourth circuitry, said translating circuitry translating information to the selected one of the plurality of prescribed formats.

5. The source channel as claimed in claim 1 in which the the source channel places information into the information stream.

6. The source channel as claimed in claim 1 wherein said first circuitry further comprises a register for storing information designating the selected one of the plurality of prescribed formats.

7. The source channel as claimed in claim 1 in which the control information is supplied by a processor of the computer system, wherein the control information includes information specifying a location of a second component where the information stream is to be placed, the second component is coupled to the destination channel and the processor is coupled to the interconnect.

8. The source channel as claimed in claim 1 in which the first circuitry comprises circuitry for varying a portion of the elements of the information stream to indicate the format.

9. The source channel as in claim 1 wherein said destination channel is coupled to the second component which comprises a frame buffer and wherein said first component comprises a video input device which provides a source of information which produces said information stream, and wherein data representative of said information stream is stored in said frame buffer.

10. A source channel as in claim 1 wherein the destination channel controls transfer of the information stream form the interconnect to the second component, which is coupled to the destination channel, in response to control information.

11. A destination channel for use in a computer system, said computer system having a source channel coupled to a first component and an interconnect, the destination channel comprising:

first circuitry coupled to the interconnect, said first circuitry receiving an information stream in any of a plurality of prescribed formats from the interconnect;

second circuitry coupled to the interconnect, said second circuitry receiving control information from a processor apart from the information stream; and

third circuitry coupled to the interconnect and a second component, said third circuitry controlling transfer of the information stream to the second component in response to the control information when the destination channel is designated as an address for the information stream by the source channel, wherein the second component and the destination channel are separately addressable.

12. The destination channel of claim 11 in which the third circuitry comprises:

fourth circuitry coupled to the interconnect and storing information from the information stream;

fifth circuitry coupled to the interconnect and selecting a starting point in the information stored in the fourth circuitry; and

fifth circuitry coupled to the interconnect and selecting an ending point in the information stored by the fourth circuitry.

13. The destination channel of claim 11 in which the second component includes a frame buffer and the destination channel is operable to load the frame buffer with the information stream in response to the control information.

14. The destination channel of claim 11 further comprising translating circuitry coupled to the interconnect and the second component, said translating circuitry translating the information stream from the selected one of the plurality of prescribed formats to another format.