Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers

• US 5,655,110 A
• Filed: 05/31/1995
• Issued: 08/05/1997
• Est. Priority Date: 02/13/1995
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran, Heavlin, William D., Kyser, David F.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Walker, Tyrone V.
• Application Number:
  US08/456,938
• Time in Patent Office: 797 Days
• Field of Search: 364/151, 364/153, 364/156, 364/158, 364/468, 364/488, 364/489, 364/490, 364/551.01, 364/578, 395/500
• US Class Current: 700/95
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/32182 If state of tool, product deviates from standard, adjust system, feedback
• CPC Class Codes: G05B 2219/32191 Real time statistical process monitoring
• CPC Class Codes: G05B 2219/45026 Circuit board, pcb
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.

Claims

1. A wafer processing system comprising:

(a) a mass-production line that processes wafers that are to have a mask-defined circuit layout, said processing occurring on a mass-production basis;

(b) sample-and-measure means for sampling processed wafers flowing through the mass-production line and for measuring and storing the values of critical dimensions of the sampled wafers;

(c) a machine-implemented, matched process model that is calibrated by use of the stored values of critical dimensions of the sampled wafers to model the behavior of the mass-production line with respect to the mask-defined circuit layout;

(d) consultor means for consulting the matched process model to predict the statistical behavior of the mass-production line for large numbers of wafers at various settings of process parameters and various tolerance allowances in those process parameters; and

(e) expert control means, operatively coupled to the sample-and-measure means, to the consultor means, and to the mass-production line, for detecting undesired variances in the statistical distribution of the processed wafer outflow of the mass-production line, for querying the consultor means to identify the most likely contributing causes for said undesired variances, and for responsively adjusting the settings of process parameters and/or the tolerance allowances of those process parameters that are identified as being the most likely contributing causes for said undesired variances;

(d.1) wherein said consultor means includes a best leveraging analyzer.

2. A wafer processing system according to claim 1 wherein said mass-production line includes a stepper and a development station.

3. A wafer processing system according to claim 1 wherein said matched process model includes:

a process simulator; and

a post-simulation calibratable transform module for transforming the simulator output signals and outputting calibrated simulation result signals closely matching corresponding result values stored in said sample-and-measure means for corresponding settings of process parameters.

4. A wafer processing system according to claim 1 wherein said matched process model includes:

an RSM/kriging module for more quickly emulating the behavior of the process simulator.

5. A wafer processing system according to claim 1 wherein said consultor means includes a prominent signal analyzer.

6. A wafer processing system comprising:

(a) a mass-production line for processing one or more lots of wafers, each wafer being processed to form a predefined circuit layout repeatedly thereon, the predefined circuit layout having at least one critically-dimensioned feature that defines operational characteristics of the corresponding circuit,

wherein the mass-production line has a plurality of controllable process parameters with each said controllable process parameter having a respective mean setting and a respective variance as seen by in-process wafers of said one or more lots of wafers;

(b) sample-and-measure means for sampling in-process wafers flowing through a given part of the mass-production line and for measuring and recording dimensions of prespecified features of the sampled wafers;

(c) a machine-implemented, matched process model that is defined by use of the recorded dimensions to model the statistical behavior of the mass-production line at least with respect to the dimensions of prespecified features of the sampled wafers,

(c.1) wherein the matched process model includes programmable, mean-and-variance modeling means for modeling respective mean settings and respective variances of a respective one or more of the controllable process parameters of said mass-production line; and

(d) consultor means for temporarily modifying respective combinations of modeled mean setting and modeled variance of a respective one or more of the controllable process parameters so as to thereby cause the temporarily modified process model to predict the statistical behavior of the mass-production line, at least with respect to the dimensions of the prespecified features, for large numbers of wafers, given the modified combinations of respective mean settings and respective variances.

7. A wafer processing system according to claim 6 wherein:

said mass-production line includes;

(a.1) coating means for forming one or more material layers on in-process wafers,

(a.2) radiation exposing means for receiving in-process wafers from the coating means and for exposing one or more of said material layers of the received in-process wafers to patterning radiation in accordance with said predefined circuit layout;

(a.3) developing means for receiving in-process wafers from the exposing means and for developing the exposed one or more material layers; and

(a.4) post-development processing means for receiving in-process wafers from the developing means and for further processing the developed wafers;

(a.5) wherein one or more of said coating, exposing, developing and post-development processing means has controllable process parameters defining at least a first and second of said controllable process parameters of the mass-production line;

(a.6) wherein said first and second controllable process parameters each has a respective mean setting and a respective variance as seen by said in-process wafers of the one or more lots of wafers;

(c.1a) said mean-and-variance modeling means models at least the respective mean settings and respective variances of the first and second controllable process parameters; and

(d.1) said consultor means includes means for temporarily modifying the respective combinations of modeled mean setting and modeled variance of the respective first and second controllable process parameters.

8. A wafer processing system according to claim 7 wherein said first and second controllable process parameters are selected from the group consisting of:

(a.1a) an anti-reflection coating (ARC) layer thickness provided by said coating means;

(a.1b) an ARC refractive index provided by said coating means;

(a.1c) a photoresist thickness provided by said coating means;

(a.2a) a focus depth of said radiation exposing means;

(a.2b) an exposure energy dosage provided by said radiation exposing means;

(a.2b'"'"') an exposure intensity provided by said radiation exposing means;

(a.2b") an exposure duration provided by said radiation exposing means;

(a.2c) a partial coherence of exposure radiation provided by said radiation exposing means;

(a.2d) a minimum patterning dimension provided by said radiation exposing means;

(a.2e) a coefficient of thermal expansion of the radiation exposing means;

(a.2f) a numeric aperture provided by said radiation exposing means;

(a.2g) a lens curvature provided by said radiation exposing means;

(a.2h) a phase shift angle provided by said radiation exposing means;

(a.3a) a development time provided by said developing means;

(a.3b) a development temperature provided by said developing means; and

(a.3c) a diffusion length provided by said developing means.

9. A wafer processing system according to claim 8 wherein said post-development processing means includes a plasma etching means and the first and second controllable process parameters are additionally selectable from the group consisting of:

(a.4a) a chamber pressure provided by said etching means;

(a.4b) a flow rate provided by said etching means;

(a.4c) a temperature provided by said etching means;

(a.4d) a field intensity provided by said etching means; and

(a.4e) an etch time provided by said etching means.

10. A wafer processing system according to claim 6 wherein:

(a.1) said at least one critically-dimensioned feature includes a transistor gate; and

(b.1) said dimensions of prespecified features of the sampled wafers include widths of conductive lines that do not define transistor gates in the corresponding circuits.

11. A wafer processing system according to claim 10 wherein:

(b.2) conductive lines include lines located in in-scribe areas of the wafers.

12. A wafer processing system according to claim 6 wherein said mean-and-variance modeling means comprises:

(c.1a) first memory means for storing said modeled mean settings;

(c.1b) second memory means for storing said modeled variances;

(c.1c) one or more random number generators, responsive to the modeled variances stored in said second memory means, for outputting respective random number samples;

(c.1d) one or more summing units for receiving modeled mean settings from the first memory means, for receiving random number samples from the one or more random number generators, and for adding respective ones of the received mean settings and respective ones of the received random number samples to thereby generate simulated process parameter signals representing a simulated one or more of the controllable process parameters.

13. A wafer processing system according to claim 12 wherein said matched process model further includes:

(c.2) a first process simulator operatively coupled to receive said simulated process parameter signals and to model a response of said mass-production line to the controllable process parameters represented by the simulated process parameter signals.

14. A wafer processing system according to claim 13 wherein:

(c.2a) said first process simulator simulates a lithography process of the mass-production line.

15. A wafer processing system according to claim 13 wherein:

(c.2a) said first process simulator defines a slow-to-evaluate simulator;

(c.3) said matched process model further includes a faster-to-evaluate second simulator that is bootstrap-wise created by use of the slow-to-evaluate simulator, said faster-to-evaluate second simulator providing a substantially equivalent process simulation as does the slow-to-evaluate first simulator in less time for a given subset of the simulated process parameter signals; and

(c.4) said matched process model further includes replacement means for replacing the slow-to-evaluate first simulator with the faster-to-evaluate second simulator when the simulated process parameter signals are within said given subset.

16. A wafer processing system according to claim 15 wherein the faster-to-evaluate second simulator includes a response surface modeler (RSM).

17. A wafer processing system according to claim 15 wherein the faster-to-evaluate second simulator includes a kriging error-correction interpolator.

18. A wafer processing system according to claim 15 wherein the faster-to-evaluate second simulator includes a response surface modeler (RSM) and an error-correction interpolator coupled to an output of the RSM for correcting errors between outputs of the RSM and outputs of the slow-to-evaluate first simulator.

19. A wafer processing system according to claim 6 further comprising:

(e) expert control means, operatively coupled to the sample-and-measure means, to the consultor means, and to the mass-production line, for detecting undesired variances in the statistical distribution of the processed wafer outflow of the mass-production line, for querying the consultor means to identify the most likely contributing causes for said undesired variances, and for responsively adjusting the settings of process parameters and/or the tolerance allowances of those process parameters that are identified as being the most likely contributing causes for said undesired variances.

20. A wafer processing system according to claim 6 further comprising:

(e) expert control means, operatively coupled to the sample-and-measure means and to the consultor means,

(e.1) said expert control means being for automatically detecting an undesired change in statistical distribution of said measured dimensions of the prespecified features of the sampled wafers, and

(e.2) said expert control means further being for querying the consultor means to identify the most likely contributing factors for the detected undesired change of statistical distribution, the contributing factors being selected from among said modeled respective mean settings and respective variances of the respective one or more of the controllable process parameters.

21. A wafer processing system according to claim 20 wherein said expert control means includes:

(e.3) first profile receiving means for receiving a first data set representing an acceptable statistical distribution profile for the at least one critically-dimensioned feature;

(e.4) second profile receiving means for receiving a second data set representing the observed statistical distribution profile of the measured dimensions of prespecified features;

(e.5) extrapolating means for extrapolating from the received second data set an estimation of what the corresponding statistical distribution profile is on the sampled wafers for the critically-dimensioned features of the sampled wafers; and

(e.6) testing means for testing the extrapolated profile against the acceptable profile.

22. A wafer processing system according to claim 21 wherein:

(d.1) said consultor means has a first mode of operation wherein the consultor means temporarily modifies corresponding combinations of modeled mean setting and modeled variance of a respective one or more of the controllable process parameters so as to thereby cause the temporarily modified process model to predict the statistical behavior of the mass-production line with respect to the critically-dimensioned features; and

(e.5a) said extrapolating means uses the first mode of operation of the consultor means for extrapolating from the received second data set the estimation of what the corresponding statistical distribution profile is on the sampled wafers for the critically-dimensioned features of the sampled wafers.

23. A wafer processing system according to claim 6 further comprising:

(e) automatic, matched-process-model creating means for supplying to a prototype of the process model, actually measured process parameters from the production line, for obtaining corresponding actually-observed results from the production line, and for modifying the prototype of the process model so that outputs of the modified prototype more closely match the actually-observed results.

24. A wafer processing system according to claim 23 wherein

the process model includes:

(c.2) a process simulator that outputs simulator output signals; and

(c.3) a post-simulation calibratable transform module for transforming the simulator output signals and correspondingly outputting calibrated simulation result signals;

and wherein said matched-process-model creating means includes;

(e.1) calibrating means for comparing the simulator output signals with the actually-observed results from the production line, and for modifying the transform module so that outputs of the modified prototype more closely match the actually-observed results.

25. A wafer processing system comprising:

(a) a mass-production line for processing a plurality of wafers to produce from each wafer a plurality of devices, each said wafer being processed by the line to form a predefined layout of features repeatedly on the wafer, the predefined layout having at least one critically-dimensioned feature that defines operational characteristics of each correspondingly produced device of the wafer,

wherein the mass-production line has a plurality of controllable process parameters with each said controllable process parameter having a respective mean and a respective variance as seen by in-process devices of each of said wafers;

(b) sampling means for obtaining from in-process wafers flowing through the mass-production line, sample measurements of prespecified features of the in-process wafers;

(c) a machine-implemented, process model that models the statistical behavior of the mass-production line at least with respect to said prespecified features,

said model having one or more modifiable inputs corresponding to a respective one or more of the controllable process parameters of the mass-production line; and

(d) a machine-implemented consultor means for temporarily disturbing one or more of the modifiable inputs of said model so as to thereby cause the temporarily disturbed process model to predict the statistical behavior of the mass-production line, at least with respect to the measured features given the temporary disturbing of said modifiable inputs.

26. A wafer processing system according to claim 25 wherein:

(a.1) said devices are integrated circuits each formed in a respective one of plural in-die areas of the wafers;

(b.1) said prespecified features are formed within in-scribe areas of the wafers, the in-scribe areas being interposed between the in-die areas.

27. A wafer processing system according to claim 25 wherein:

(a.1) said at least one critically-dimensioned feature of the predefined layout is an electrically conductive first structure having at least one of a respective first width, first thickness;

(b.1) said sampled prespecified features are each a second electrically conductive structure that is formed simultaneously with the corresponding at least one critically-dimensioned feature of the predefined layout and that has at least one of a corresponding second width, second thickness, and second sidewall slope; and

(b.2) said sample measurements include at least one of the second width, second thickness, and second sidewall slope of the sampled prespecified features.

28. A wafer processing system according to claim 25 wherein:

(a.1) said at least one critically-dimensioned feature is a developed photoresist structure.

29. A wafer processing system according to claim 25 wherein said machine-implemented process model comprises:

(c.1) first modifiable memory means for storing modeled mean settings representing statistical means of the respective one or more controllable process parameters of the mass-production line;

(c.2) second modifiable memory means for storing modeled variances representing statistical variances of the respective one or more controllable process parameters of the mass-production line;

(c.3) random number generating means, responsive to the modeled variances for outputting respective random number samples;

(c.4) summing means for summing respective ones of the modeled mean settings with corresponding ones of the random number samples to thereby generate simulated process parameter signals representing simulations of one or more of the controllable process parameters.

30. A wafer processing system according to claim 29 wherein said machine-implemented process model receives as its modifiable inputs in a first mode said generated simulated process parameter signals and wherein said model further comprises:

(c.5) a process simulator that outputs simulator output signals in response to the received modifiable inputs; and

(c.6) a post-simulation calibratable transform module for transforming the simulator output signals and for correspondingly outputting calibrated simulation result signals in accordance with a transformation that is calibratable to correspond with observed inputs and observed corresponding outputs of the mass-production line.

31. A wafer processing system according to claim 25 wherein said consultor means includes:

(d.1) prominent signal analyzer means for temporarily resetting modeled ones of the modifiable inputs one at a time to a null value.

32. A wafer processing system according to claim 25 wherein said consultor means includes:

(d.1) best leveraging analyzer means for sequentially selecting and modifying respective ones of the modifiable inputs one at a time in accordance with which modifiable input provides best leverage at the time for moving a modeled behavior of the mass-production line towards a predefined.

33. A wafer processing system according to claim 32 wherein said modeled behavior to be moved is variance of the at least one critically-dimensioned feature as seen across the produced devices.

34. A machine-implemented simulation system comprising:

(a) a slow-to-evaluate first simulator;

(b) a fast-to-evaluate second simulator that can be programmed to generate second results substantially equal to first results of the first simulator in less time than does the slow-to-evaluate first simulator when the so-programmed second simulator is given input parameters within a predefined range;

(c) bootstrapping means, responsive to results of the first simulator, for programming the fast-to-evaluate second simulator to generate said second results in response to input parameters within said predefined range; and

(d) substituting means for substituting the programmed second simulator in place of the slow-to-evaluate first simulator.

35. A simulation system according to claim 34 wherein said bootstrapping means includes:

(c.1) drive means supplying a series of input parameter sets distributed through said predefined range to the slow-to-evaluate first simulator to thereby cause the first simulator to produce said first results; and

(c.2) result storage means for storing the produced first results of the slow-to-evaluate first simulator.

36. A simulation system according to claim 35 wherein said drive means includes a Latin-hypercube driving engine.

37. A simulation system according to claim 34 wherein said fast-to-evaluate second simulator includes a response surface modeler (RSM).

38. A simulation system according to claim 34 wherein said fast-to-evaluate second simulator includes an error-correction interpolator.

39. A simulation system according to claim 34 wherein said slow-to-evaluate first simulator simulates a photolithographic process.