Method and apparatus for control of power consumption in a computer system

• US 5,655,127 A
• Filed: 03/08/1996
• Issued: 08/05/1997
• Est. Priority Date: 02/04/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bhatt, Ajay V., Shah, Nilesh V., Kardach, James P., Bogin, Zohar, Rabe, Jeffrey L.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/612,673
• Time in Patent Office: 515 Days
• Field of Search: 395/750, 395/838, 395/868, 395/734
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

Claims

1. A computer system having a full-power mode and a low-power mode of operation comprising:

a controller that generates an interrupt signal in response to a low power event or a fully operational event, the controller further generates a clock control signal, wherein the clock control signal is alternatively asserted for a first time duration and deasserted for a second time duration during the low-power mode of operation and the clock control signal is deasserted during the full-power mode of operation;

a processor coupled to the controller, wherein the processor suppresses an internal clock signal to at least one functional block within the processor in response to an asserted clock control signal and transmits the internal clock signal to the at least one functional block within the processor in response to a deasserted clock control signal; and

a communication device coupled to the processor, wherein the communication device periodically provides communication signals to the processor, and wherein the processor is responsive to the communication device during the low-power mode of operation when the interval between two consecutive communication signals is greater than the sum of the first time duration and the second time duration.

2. The computer system of claim 1, wherein the controller includes a first register, a second register, and a state machine, further wherein the first register stores the first time duration and provides a first input signal to the state machine, the second register stores the second time duration and provides a second input signal to the state machine, the state machine receives an enable signal and alternatively generates an asserted clock control signal for the first time duration and a deasserted clock control signal for the second time duration in response to an asserted enable signal.

3. The computer system of claim 2, wherein the controller further includes a break event selection device coupled to the state machine, the break event selection device including at least one break event input that is capable of receiving the break event signal, when at least one of the break event inputs receive a break event signal that corresponds to a selected break event, the break event selection device provides a third input signal to the state machine, and the state machine causes the clock control signal to be immediately deasserted for at least the second time duration.

4. The computer system of claim 1, wherein the fully operational event includes a mouse movement, a keyboard entry, or a real-time clock signal.

5. The computer system of claim 1, wherein the low power event includes a count-down signal or a real-time clock signal.

6. The computer system of claim 1, wherein the controller further includes a low power/fully operational event selection device having at least one low power/fully operational event input that is capable of receiving a low power event signal or a fully operational event signal, when the low power/fully operational event selection device receives the low power event signal that corresponds to a selected low power event while in the full-power mode of operation, the switching device generates the interrupt signal to transition the computer system from the full-power mode to the low-power mode of operation, and when the low power event/fully operational event selection device receives the fully operational event signal that corresponds to a selected fully operational event while in the low-power mode of operation, the switching device generates the interrupt signal to transition the computer system from the low-power mode to the full-power mode of operation.

7. A method for controlling the power consumption of a computer system which includes a processor coupled to a communication device that periodically provides communication signals to the processor, the processor having a full-power mode and a low-power mode of operation, the method comprising the steps of:

(a) operating the processor in a full-power mode of operation;

(b) storing a set of functional parameters which specify a low power event and a fully operational event; and

(c) switching the processor from the high-power mode of operation to the low-power mode of operation in response the low power event by alternatively asserting for a first time duration and deasserting for a second time duration a clock control signal, wherein a clock signal coupled to at least one functional block within the processor is suppressed in response to an asserted clock control signal and transmitted in response to a deasserted clock control signal, wherein the processor remains responsive to communication signals during the low-power mode of operation when the interval between two consecutive communication signals is greater than the sum of the first time duration and the second time duration.

8. The method of claim 7, further comprises the step of:

(d) switching the processor back to the full-power mode of operation in response to the fully operational event by deasserting the clock control signal,

wherein the clock signal coupled to the at least one functional block within the processor is transmitted in response to the deasserted clock control signal.

9. The method of claim 8, wherein step (d) further comprises the step of modifying the functional parameters which define the low-power event.

10. The method of claim 8 wherein step (d) further comprises the step of clearing the enable bit.

11. The method of claim 7 wherein step (c) further comprises the steps of:

(i) storing the first time duration in a first register and storing the second time duration in a second register; and

(ii) setting an enable bit that controls the assertion and deassertion of the clock control signal.

12. The method of claim 7 wherein step (c) further comprises the steps of modifying the functional parameters which define the high-power event.

13. A computer system having a full-power mode and a low-power mode of operation comprising:

a processor having a controller and at least one functional block, wherein the controller generates an interrupt signal in response to a low power event or a fully operational event, and further generates a clock control signal, wherein the clock control signal is alternatively asserted for a first time duration and deasserted for a second time duration during the low-power mode of operation and the clock control signal is deasserted during the full-power mode of operation, and further wherein at least one of the functional blocks receive an internal clock signal in response to a deasserted clock control signal; and

a communication device coupled to the processor, wherein the communication device periodically provides communication signals to the processor, and the processor is responsive to the communication device during the low-power mode of operation when the interval between two consecutive communication signals is greater than the sum of the first time duration and the second time duration.

14. The computer system of claim 13, wherein the controller includes a first register, a second register, and a state machine, wherein the first register stores the first time duration and provides a first input signal to the state machine, the second register stores the second time duration and provides a second input signal to the state machine, and the state machine receives an enable signal and alternatively generates an asserted clock control signal for the first time duration and a deasserted clock control signal for the second time duration in response to an asserted enable signal.

15. The computer system of claim 14, wherein the clock controller further includes a break event selection device coupled to the state machine, wherein the break event selection device includes at least one break event input that is capable of receiving a break event signal, and when at least one of the break event inputs receive a break event signal that corresponds to a selected break event, the break event selection device provides a third input signal to the state machine, and wherein the state machine causes the clock control signal to be immediately deasserted for at least the second time duration.

16. The computer system of claim 13, wherein the switching device includes a low power/fully operational event selection device having at least one low power/fully operational event input that is capable of receiving a low power event signal or a fully operational event signal, when the low power/fully operational event selection device receives the low power event signal that corresponds to a selected low power event while in the full-power mode of operation, the switching device generates the interrupt signal to transition the computer system from the full-power mode to the low-power mode of operation, when the low power event/fully operational event selection device receives the fully operational event signal that corresponds to a selected fully operational event while in the low-power mode of operation, the switching device generates the interrupt signal to transition the computer system from the low-power mode to the full-power mode of operation.

17. The computer system of claim 13, wherein the fully operational event includes a mouse movement, a keyboard entry, or a real-time clock signal.

18. The computer system of claim 13, wherein the low power event includes a count-down signal or a real-time clock signal.