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Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation

  • US 5,655,145 A
  • Filed: 10/25/1994
  • Issued: 08/05/1997
  • Est. Priority Date: 10/20/1992
  • Status: Expired due to Fees
First Claim
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1. An interface circuit for transferring data between a host device coupled to a compute bus and a peripheral device coupled to a peripheral device bus, said interface circuit coupled to said computer bus and said peripheral device bus, said interface circuit comprising:

  • an address decoder having an input coupled to said computer bus, and having an output;

    a configuration register having an input coupled to said output of said address decoder, and having an outputa controlling state machine having an input coupled to said output of said configuration register;

    a host data receiving circuit coupled to said computer bus and said peripheral device bus for receiving said data from said computer bus and transferring said data to said peripheral device bus, said transfer of said data from said computer bus to said host data receiving circuit not being a DMA transfer;

    means coupling said controlling state machine to said host data receiving circuit, wherein said controlling state machine includes means which responds to a write data command of a first protocol type received from said computer bus by producing a control signal which is provided to said host data receiving circuit to transfer said data from said host data receiving circuit to said peripheral device bus according to a second data transfer protocol which is not supported by said computer bus, said second data transfer protocol being a DMA protocol.

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