SCSI host adapter integrated circuit utilizing a sequencer circuit to control at least one non-data SCSI phase without use of any processor
First Claim
1. A host adapter integrated circuit for use in a host computer system having a host computer bus, a host processor for executing user instructions, and a SCSI bus having a set of data lines and a set of control lines, and for transfer of data between a host computer data bus of said host computer bus, and said SCSI bus via a SCSI protocol that includes a sequence of SCSI phases, said host adapter integrated circuit comprising:
- a sequencer circuit having a first plurality of control lines coupled to said host computer bus and a second plurality of control lines connected to said set of control lines of said SCSI bus;
wherein said sequencer circuit controls at least one SCSI phase that is different from a SCSI data phase in said sequence of SCSI phases and completes said at least one SCSI phase without use of any processor; and
a hardware interrupt circuit having an input line connected to said sequencer circuit and an interrupt output line;
wherein upon receipt of a signal on said input line, said hardware interrupt circuit generates a hardware interrupt signal on said interrupt output line for said host processor, and further wherein upon receipt of said hardware interrupt, said host processor suspends operation of any program executing in said host computer system, and uses said host adapter integrated circuit to perform another SCSI phase of operations in said sequence of SCSI phases for transferring data between said host computer data bus and said set of data lines of said SCSI bus.
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Accused Products
Abstract
A single chip circuit is used in combination with a host system microprocessor to provide host-adapter functions for a SCSI interface. The host adapter integrated circuit includes a 128 byte DMA FIFO, a 8 byte SCSI FIFO, hardwired automatic sequencers for the SCSI ARBITRATION and SELECTION phases, hardware interrupt generating circuitry, two clock sources, a register set and a powerdown capability. The host computer system microprocessor is used to perform selected SCSI phases. Other SCSI phases are performed automatically by the integrated circuit of this invention. When a delay in a SCSI phase is anticipated, according to the principles of this invention control of the microprocessor is returned to the host computer system. Hence, the microprocessor may execute a user application while the integrated circuit simultaneously performs one or more SCSI phases. When the SCSI phase is complete or other predetermined conditions occur on the SCSI bus, a hardware interrupt is sent to the microprocessor. In response to the interrupt, the microprocessor is available to support further SCSI operations by the integrated circuit of this invention.
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Citations
52 Claims
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1. A host adapter integrated circuit for use in a host computer system having a host computer bus, a host processor for executing user instructions, and a SCSI bus having a set of data lines and a set of control lines, and for transfer of data between a host computer data bus of said host computer bus, and said SCSI bus via a SCSI protocol that includes a sequence of SCSI phases, said host adapter integrated circuit comprising:
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a sequencer circuit having a first plurality of control lines coupled to said host computer bus and a second plurality of control lines connected to said set of control lines of said SCSI bus; wherein said sequencer circuit controls at least one SCSI phase that is different from a SCSI data phase in said sequence of SCSI phases and completes said at least one SCSI phase without use of any processor; and a hardware interrupt circuit having an input line connected to said sequencer circuit and an interrupt output line; wherein upon receipt of a signal on said input line, said hardware interrupt circuit generates a hardware interrupt signal on said interrupt output line for said host processor, and further wherein upon receipt of said hardware interrupt, said host processor suspends operation of any program executing in said host computer system, and uses said host adapter integrated circuit to perform another SCSI phase of operations in said sequence of SCSI phases for transferring data between said host computer data bus and said set of data lines of said SCSI bus. - View Dependent Claims (3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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2. A host/adapter system, for use in a host computer system having a host processor for executing user instructions, and for interfacing a host computer data bus of a host computer bus with a SCSI bus, that includes a set of data lines and a set of control lines, for transfer of data between said host computer data bus and said SCSI bus via a SCSI protocol that includes a sequence of SCSI phases, said host/adapter system comprising:
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host adapter BIOS and service means including a SCSI manager means; and
a driver means coupled to said SCSI manager means, wherein said driver means is for loading into a memory of said host computer system wherein said memory is coupled to said host processor of said host computer system, and for controlling data transfer between said computer data bus and said SCSI bus by sending instructions to said host processor which in turn generates information; anda host adapter integrated circuit including; a sequencer circuit having a first plurality of control lines coupled to said host computer bus wherein said first plurality of control lines (i) receive signals in response to signals from said driver means including said information, and (ii) provide signals which in turn are transmitted to said driver means; and
a second plurality of control lines connected to said set of control lines of said SCSI bus;wherein said sequencer circuit, in response to signals on said first plurality of control lines, controls at least one SCSI phase that is different from a SCSI data phase in said sequence of SCSI phases; and
said driver means returns control of said host processor to said host computer system, and said sequencer circuit completes said at least one SCSI phase in said sequence of SCSI phases without use of any processor; anda hardware interrupt circuit having an input line connected to said sequencer circuit, and an interrupt output line; wherein upon receipt of a signal on said input line, said hardware interrupt circuit generates a hardware interrupt signal on said interrupt output line for said host processor, and further wherein upon receipt of said interrupt signal, said host processor suspends operation of any program executing in said host computer system, and uses said host adapter integrated circuit to perform another SCSI phase in said sequence of SCSI phases. - View Dependent Claims (8)
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27. An host adapter integrated circuit, for use in a host computer system having a host computer bus and a host processor for executing user instructions, and for transferring data between a host computer data bus of said host computer bus and a SCSI bus having a set of data lines and a set of control lines, said host adapter integrated circuit comprising:
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a hardware sequencer circuit connected to said set of control lines of said SCSI bus, and coupled to said host computer bus, and responsive to information from a driver means wherein said hardware sequencer circuit controls each SCSI phase of a plurality of SCSI phases, and further wherein upon providing information to said hardware sequencer circuit, such a driver means returns control of said processor to said computer system, and said hardware sequencer circuit completes at least one SCSI phase without use of any processor; a SCSI interrupt circuit coupled to said set of control lines of said SCSI bus, and coupled to said hardware sequencer circuit wherein said SCSI interrupt circuit generates SCSI interrupts indicating the status of said SCSI bus, and indicating completion of a SCSI phase; and a host processor interrupt circuit connected to said SCSI interrupt circuit, wherein said host processor interrupt circuit generates a hardware interrupt for said host processor in response to said SCSI interrupt circuit indicating completion of a SCSI phase wherein upon receipt of said hardware interrupt, said host processor suspends operation of any program executing in said host computer system. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. In a host computer system including a host computer data bus, a host processor, and an host adapter integrated circuit having (a) hardwired sequencers for performing predetermined SCSI phases upon programming of said host adapter integrated circuit and (b) a hardware interrupt generating circuit for generating a hardware interrupt upon one of (i) completion of a predetermined SCSI phase, and (ii) predetermined conditions on a SCSI bus having a set of data lines and a set of control lines, a method for transferring data between said host computer data bus and said set of data lines of said SCSI bus comprising:
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programming by means of said host processor at least one of said hardwired sequencers to perform at least one SCSI phase wherein said at least one of said hardwired sequencers is connected to said set of control lines of said SCSI bus; returning control of said host processor to said host computer system; performing said at least one SCSI phase using said programmed at least one of said hardwired sequencers connected to said set of control lines of said SCSI bus without further use of any processor; and generating a hardware interrupt for said host processor upon completion of said at least one SCSI phase wherein upon receipt of said hardware interrupt, said host processor suspends operation of any program executing in said host computer system. - View Dependent Claims (48, 49, 50, 51, 52)
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Specification