Method for forming three dimensional processor using transferred thin film circuits

• US 5,656,548 A
• Filed: 09/19/1995
• Issued: 08/12/1997
• Est. Priority Date: 09/30/1993
• Status: Expired due to Term

• Current Assignee: Alanzor Research AB LLC (Intellectual Ventures LLC)
• Original Assignee: Kopin Corporation
• Inventors: Zavracky, Matthew, Vu, Duy-Phach, Dingle, Brenda, Zavracky, Paul M.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/531,177
• Time in Patent Office: 693 Days
• Field of Search: 437/208, 437/205, 437/915, 437/21, 257/700, 257/666, 257/723, 257/724, 148/164
• US Class Current: 438/23
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/164 : Three dimensional processing

Abstract

A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

Claims

1. A method of fabricating a data processor comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a second circuit of a data processor in a second layer of semiconductor material;

bonding the second layer to the first layer with a bonding layer;

forming an opening in the bonding layer for an interconnect; and

connecting the first data processor circuit with the second data processor circuit with an interconnect extending through the bonding layer opening such that data processor signals can be conducted between the first data processor circuit and the second data processor circuit.

2. The method of claim 1 further comprising forming a controller in the first circuit or the second circuit.

3. The method of claim 1 further comprising forming a memory in the first circuit or the second circuit.

4. The method of claim 1 further comprising bonding the first circuit layer to the second circuit layer with a polymeric adhesive.

5. The method of claim 1 further comprising forming the second circuit in a thin film semiconductor layer on an insulating substrate.

6. The method of claim 5 further comprising transferring the thin film semiconductor layer and attached insulating layer onto the first layer of semiconductor layer.

7. The method of claim 1 wherein the first layer of semiconductor material comprises a bulk semiconductor wafer.

8. The method of claim 1 wherein the first circuit layer or the second circuit layer comprises silicon.

9. The method of claim 1 wherein the first circuit layer or the second circuit layer comprises a III-V material.

10. The method of claim 1 further comprising forming a third circuit layer over the second circuit layer.

11. The method of claim 1 further comprising forming a plurality of additional circuit layers over the first and second circuit layers.

29. The method of claim 1 further comprising transferring the second layer to the first layer with a single transfer process.

30. The method of claim 1 further comprising transferring the second layer to the first layer with a double transfer process.

31. The method of claim 1 further comprising forming the layers with a silicon-on-insulator (SOI) film.

12. A method of fabricating a data processor comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a light emitting device in a second layer of semiconductor material;

bonding the second layer to the first layer with a bonding layer;

forming an opening in the bonding layer for an interconnect; and

connecting the first data processor circuit with the light emitting device with an interconnect extending through the bonding layer opening such that data processor signals can be conducted between the first data processor circuit and the light emitting device.

13. The method of claim 12 further comprising forming a controller in the first circuit.

14. The method of claim 12 further comprising forming a memory in the first circuit.

15. The method of claim 12 further comprising bonding the first circuit layer to the second layer with a polymeric adhesive.

16. The method of claim 12 further comprising forming the light emitting device in a thin film semiconductor layer on an insulating substrate.

17. The method of claim 12 further comprising transferring the thin film semiconductor layer and attached insulating layer onto the first layer of semiconductor layer.

18. The method of claim 12 wherein the first layer of semiconductor material comprises a bulk semiconductor wafer.

19. The method of claim 12 wherein the first circuit layer comprises silicon.

20. The method of claim 12 wherein the first circuit layer or the second circuit layer comprises a III-V material.

26. The method of claim 12 further comprising transferring the second layer to the first layer with a single transfer process.

27. The method of claim 12, further comprising transferring the second layer to the first layer with a double transfer process.

28. The method of claim 12 further comprising forming the layers with a silicon-on-insulator (SOI) film.

62. The method of claim 12 further comprising forming a third circuit layer over the second circuit layer.

63. The method of claim 12 further comprising forming a plurality of additional circuit layers between the first and second circuit layers.

21. A method of fabricating a data processor comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a circuit routing layer and bonding the circuit routing layer to the first circuit layer;

forming a second circuit of a data processor in a second layer of semiconductor material;

bonding the second layer to the circuit routing layer with a bonding layer;

forming an opening in the bonding layer for an interconnect; and

connecting the first data processor circuit with the second data processor circuit with an interconnect extending through the bonding layer opening and along the circuit routing layer such that data processor signals can be conducted between the first data processor circuit and the second data processor circuit.

22. The method of claim 21 further comprising forming a controller in the first circuit or the second circuit.

23. The method of claim 21 further comprising forming a memory in the first circuit or the second circuit.

24. The method of claim 21 further comprising bonding the first circuit layer to the second circuit layer with a polymeric adhesive.

25. The method of claim 21 further comprising tiling a plurality of second circuit layers over the circuit routing layer.

32. A method of fabricating a data processor comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a second circuit of a data processor in a second layer of semiconductor material;

bonding the second layer to the first layer with a bonding layer;

curing said bonding layer;

forming a hole through the bonding layer; and

applying a metallization layer for electrically connecting the first circuit and the second circuit, the metallization layer flowing from the second layer through the hole to the first layer.

33. The method of claim 32 further comprising forming the layers with a silicon-on-insulator (SOI) film.

34. The method of claim 32 wherein the first circuit layer or the second circuit layer comprises silicon.

35. The method of claim 32 wherein the first circuit layer or the second circuit layer comprises a III-V material.

36. The method of claim 32 further comprising forming a plurality of additional circuit layers over the first and second circuit layers.

37. The method of claim 32 further comprising tiling a plurality of second circuit layers over the circuit routing layer.

38. The method of claim 32 further comprising forming the second circuit in a thin film semiconductor layer on an insulating substrate.

39. The method of claim 32 further comprising forming a plurality of additional circuit layers between the first and second circuit layers.

40. A method of fabricating a data processor, comprising:

forming a first circuit having a first data processor circuit in a first silicon layer of a first silicon-on-insulator structure;

forming a second circuit having a second data processor circuit in a second silicon layer of a second silicon-on-insulator structure;

bonding the second layer to the first layer with a bonding layer;

forming openings in the bonding layer for interconnects; and

thereafter

connecting the first data processor circuit with the second data processor circuit with interconnects extending through the openings in the bonding layer to enable communication of data processor signals between the first data processor circuit and the second data processor circuit.

41. The method of claim 40 wherein the first circuit layer or the second circuit layer comprises silicon.

42. The method of claim 40 wherein the first circuit layer or the second circuit layer comprises a III-V material.

43. The method of claim 40 further comprising forming a plurality of additional circuit layers over the first and second circuit layers.

44. The method of claim 40 further comprising forming the second circuit in a thin film semiconductor layer on an insulating substrate.

45. The method of claim 40 further comprising forming a plurality of additional circuit layers between the first and second circuit layers.

46. A method of fabricating a data processor, comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a second circuit of a data processor in a second layer of semiconductor material on a substrate;

bonding the second layer to the first layer with a bonding layer;

removing the substrate from the second layer;

forming an opening in the bonding layer for an interconnect; and

connecting the first data processor circuit with the second data processor circuit with an interconnect extending through the bonding layer opening such that data processor signals can be conducted between the first data processor circuit and the second data processor circuit.

47. The method of claim 46 further comprising forming the layers with a silicon-on-insulator (SOI) film.

48. The method of claim 46 wherein the first circuit layer or the second circuit layer comprises silicon.

49. The method of claim 46 wherein the first circuit layer or the second circuit layer comprises a III-V material.

50. The method of claim 46 further comprising forming a plurality of additional circuit layers over the first and second circuit layers.

51. The method of claim 46 further comprising tiling a plurality of second circuit layers over the circuit routing layer.

52. The method of claim 46 further comprising forming the second circuit in a thin film semiconductor layer on an insulating substrate.

53. The method of claim 46 further comprising forming a plurality of additional circuit layers between the first and second circuit layers.

54. A method of fabricating a data processor, comprising:

forming a first circuit of a data processor in a first layer of semiconductor material;

forming a second circuit of a data processor in a second layer of semiconductor material on a substrate;

transferring the second layer to a transfer body;

removing the substrate from the second layer;

bonding the second layer to the first layer with a bonding layer;

removing the transfer body from the second layer;

forming an opening in the bonding layer for an interconnect; and

connecting the first data processor circuit with the second data processor circuit with an interconnect extending through the bonding layer opening such that data processor signals can be conducted between the first data processor circuit and the second data processor circuit.

55. The method of claim 54 further comprising forming the layers with a silicon-on-insulator (SOI) film.

56. The method of claim 54 wherein the first circuit layer or the second circuit layer comprises silicon.

57. The method of claim 54 wherein the first circuit layer or the second circuit layer comprises a III-V material.

58. The method of claim 54 further comprising forming a plurality of additional circuit layers over the first and second circuit layers.

59. The method of claim 54 further comprising tiling a plurality of second circuit layers over the circuit routing layer.

60. The method of claim 54 further comprising forming the second circuit in a thin film semiconductor layer on an insulating substrate.

61. The method of claim 54 further comprising forming a plurality of additional circuit layers between the first and second circuit layers.