Method of making a thin conformal high-yielding multi-chip module

• US 5,656,552 A
• Filed: 06/24/1996
• Issued: 08/12/1997
• Est. Priority Date: 06/24/1996
• Status: Expired due to Term

• Current Assignee: National Security Agency
• Original Assignee: National Security Agency
• Inventors: Mountain, David Jerome, Hudak, John James
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Turner, Kevin F.
• Application Number:
  US08/668,879
• Time in Patent Office: 414 Days
• Field of Search: 437/206, 437/207, 437/923, 437/974, 437/225, 437/228, 148/DIG. 150, 148/DIG. 135, 257/668, 257/700
• US Class Current: 438/15
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A method of making a multi-chip module by thinning individual integrated circuit die or an integrated circuit wafer containing multiple integrated circuits; bonding thinned dice or a thinned wafer to a mylar, polyimide, semiconductor, or ceramic substrate; depositing at least one interconnect material over the wafer, where the first interconnect layer is deposited directly over the wafer; depositing a dielectric layer over each of the interconnect layers; opening vias in the dielectric layers in order to interconnect the dice and multi-chip module as required; and removing the substrate to form a thin, conformal, and high-yielding multi-chip module.

Claims

1. A method of making a multi-chip module, comprising the steps of:

a) thinning at least one integrated circuit to a thickness of less than or equal to 50 um, where the at least one integrated circuit has a circuit side and a backside;

b) testing the thinned at least one integrated circuit;

c) bonding the tested at least one thinned integrated circuit to a bonding substrate;

d) putting a layer of interconnect material directly over the at least one thinned integrated circuit and the bonding substrate;

e) putting a dielectric layer over said interconnect layer;

f) opening vias in said dielectric layer;

g) repeating steps (d), (e), and (f) for each additional interconnect layer required; and

h) removing the bonding substrate to form a multi-chip module.

2. The method of claim 1, wherein said step of thinning at least one integrated circuit comprises the steps of:

a) coating the circuit side of the at least one integrated circuit with polyimide;

b) curing the coated at least one integrated circuit a first time at a temperature of 80°

C. for one minute;

c) curing the coated at least one integrated circuit a second time at 350°

C. for one hour in a vacuum;

d) bonding a handle-wafer to the polyimide layer coated to the circuit side of the at least one integrated circuit;

.

e) thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um; and

f) removing the thinned at least one integrated circuit from the handle-wafer.

3. The method of claim 1, wherein said step of thinning at least one integrated circuit comprises the steps of:

a) bonding the at least one integrated circuit side down to a first supporting substrate in a registered fashion so that the at least one integrated circuit may be positionally identified;

b) surrounding the at least one integrated circuit with a suitable material;

c) thinning the at least one integrated circuit from the backside to a thickness of less than or equal to 50 um;

d) making electrical contact to the backside of the at least one integrated circuit as required;

e) bonding a second supporting substrate to the backside of the thinned at least one integrated circuit in order to create a three layer stack; and

f) removing the first supporting substrate.

4. The method of claim 3, wherein said step of surrounding the at least one integrated circuit is comprised of surrounding the at least one integrated circuit with a material selected from the group consisting of hard wax, epoxy, bisbenzocyclobutene resin, polyimide, and acrylic.

5. The method of claim 4, wherein said step of thinning the at least one integrated circuit is comprised of thinning the at least one integrated circuit by a thinning technique selected from the group consisting of mechanical grinding, lapping, polishing, wet chemical etching, dry chemical etching, sputter removal, and a combination thereof.

6. The method of claim 5, wherein said step of removing the first supporting substrate is comprised of removing the first supporting substrate by a removal technique selected from the group consisting of mechanical grinding, lapping, polishing, wet chemical etching, dry chemical etching, sputter removal, and a combination thereof.

7. The method of claim 2, wherein said step of thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um is comprised of thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um where said at least one integrated circuit is backside processed to form a backside electrode.

8. The method of claim 1, wherein said step of thinning at least one integrated circuit is comprised of thinning at least one integrated circuit where the at least one integrated circuit is selected from the group consisting of an unbeveled integrated circuit die, a beveled integrated circuit die, an unbeveled integrated circuit wafer, a beveled integrated circuit wafer, a segment of an unbeveled integrated circuit wafer, and a segment of a beveled integrated circuit wafer.

9. The method of claim 1, further comprising the step of beveling any unbeveled at least one integrated circuit after the at least one integrated circuit is bonded to the bonding substrate and before the interconnect layer is put on the at least one integrated circuit.

10. The method of claim 1, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate wherein said bonding substrate is selected from the group consisting of polyimide, mylar, ceramic, and semiconductor.

11. The method of claim 1, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate selected from the group consisting of a bonding substrate coated with a conducting material to provide electrical contact to a backside electrode of the tested at least one thinned integrated circuit and a bonding substrate coated with a dielectric material.

12. The method of claim 1, wherein said step of putting a layer of interconnect material directly over the at least one thinned integrated circuit and bonding substrate is comprised of putting a layer of interconnect material directly over the at least one thinned integrated circuit using a technique selected from the group consisting of depositing an interconnect layer, laser forming an interconnect layer, and laminating a pre-formed interconnect layer.

13. The method of claim 1, wherein said step of putting a layer of dielectric material over the interconnect layer is comprised of putting a layer of dielectric material over the interconnect layer using a technique selected from the group consisting of depositing dielectric material, laser forming dielectric material, and laminating pre-formed dielectric material.

14. The method of claim 1, wherein said step of bonding the tested at least one integrated circuit to a bonding substrate comprises bonding at least two tested integrated circuits to a bonding substrate.

15. The method of claim 14, wherein said step of bonding at least two tested integrated circuits to a bonding substrate comprises bonding the at least two tested integrated circuits to a bonding substrate using a technique selected from the group consisting of butting the at least two tested integrated circuits together and overlapping the at least two tested integrated circuits.

16. The method of claim 1, wherein said step of removing the bonding substrate to form a multi-chip module is comprised of removing the bonding substrate using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.

17. The method of claim 7, wherein said step of removing the thinned at least one die from the handle-wafer is comprised of removing the thinned at least one integrated circuit using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.

18. The method of claim 17, wherein said step of thinning at least one integrated circuit is comprised of thinning at least one integrated circuit where the at least one integrated circuit is selected from the group consisting of an unbeveled integrated circuit die, a beveled integrated circuit die, an unbeveled integrated circuit wafer, a beveled integrated circuit wafer, a segment of an unbeveled integrated circuit wafer, and a segment of a beveled integrated circuit wafer.

19. The method of claim 18, further comprising the step of beveling any unbeveled at least one integrated circuit after the at least one integrated circuit is bonded to the bonding substrate and before the interconnect layer is put on the at least one integrated circuit.

20. The method of claim 19, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate wherein said bonding substrate is selected from the group consisting of polyimide, mylar, ceramic, and semiconductor.

21. The method of claim 20, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate selected from the group consisting of a bonding substrate coated with a conducting material to provide electrical contact to a backside electrode of the tested at least one thinned integrated circuit and a bonding substrate coated with a dielectric material.

22. The method of claim 21, wherein said step of putting a layer of interconnect material directly over the at least one thinned integrated circuit and bonding substrate is comprised of putting a layer of interconnect material directly over the at least one thinned integrated circuit using a technique selected from the group consisting of depositing an interconnect layer, laser forming an interconnect layer, and laminating a pre-formed interconnect layer.

23. The method of claim 22, wherein said step of putting a layer of dielectric material over the interconnect layer is comprised of putting a layer of dielectric material over the interconnect layer using a technique selected from the group consisting of depositing dielectric material, laser forming dielectric material, and laminating pre-formed dielectric material.

24. The method of claim 23, wherein said step of removing the bonding substrate to form a multi-chip module is comprised of removing the bonding substrate using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.

25. A method of making a multi-chip module, comprising the steps of:

a) thinning at least one integrated circuit to a thickness of less than or equal to 50 um, where the at least one integrated circuit has a circuit side and a backside;

b) testing the thinned at least one integrated circuit;

c) bonding the tested at least one thinned integrated circuit to a bonding substrate;

d) putting a dielectric layer over said at least one thinned integrated circuit;

e) etching the dielectric layer to the surface of the at least one integrated circuit so that dielectric material remains along the edge of the at least one integrated circuit for rounding the edges of the at least one integrated circuit;

f) putting a layer of interconnect material over the at least one integrated circuit and dielectric layer at the edge of the at least one integrated circuit;

g) putting a dielectric layer over the interconnect layer;

h) repeating steps (f) and (g) for each additional interconnect layer required; and

i) removing the bonding substrate to form a multi-chip module.

26. The method of claim 25, wherein said step of thinning at least one integrated circuit comprises the steps of:

a) coating the circuit side of the at least one integrated circuit with polyimide;

b) curing the coated at least one integrated circuit a first time at a temperature of 80°

C. for one minute;

c) curing the coated at least one integrated circuit a second time at 350°

C. for one hour in a vacuum;

d) bonding a handle-wafer to the polyimide layer coated to the circuit side of the at least one integrated circuit;

e) thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um; and

f) removing the thinned at least one integrated circuit from the handle-wafer.

27. The method of claim 25, wherein said step of thinning at least one integrated circuit comprises the steps of:

a) bonding the at least one integrated circuit circuit side down to a first supporting substrate in a registered fashion so that the at least one integrated circuit may be positionally identified;

b) surrounding the at least one integrated circuit with a suitable material;

c) thinning the at least one integrated circuit from the backside to a thickness of less than or equal to 50 um;

d) making electrical contact to the backside of the at least one integrated circuit as required;

e) bonding a second supporting substrate to the backside of the thinned at least one integrated circuit in order to create a three layer stack; and

f) removing the first supporting substrate.

28. The method of claim 27, wherein said step of surrounding the at least one integrated circuit is comprised of surrounding the at least one integrated circuit with a material selected from the group consisting of hard wax, epoxy, bisbenzocyclobutene resin, polyimide, and acrylic.

29. The method of claim 28, wherein said step of thinning the at least one integrated circuit is comprised of thinning the at least one integrated circuit by a thinning technique selected from the group consisting of mechanical grinding, lapping, polishing, wet chemical etching, dry chemical etching, sputter removal, and a combination thereof.

30. The method of claim 29, wherein said step of removing the first supporting substrate is comprised of removing the first supporting substrate by a removal technique selected from the group consisting of mechanical grinding, lapping, polishing, wet chemical etching, dry chemical etching, sputter removal, and a combination thereof.

31. The method of claim 26, wherein said step of thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um is comprised of thinning the at least one integrated circuit from the backside of the at least one integrated circuit to a thickness of less than or equal to 50 um where said at least one integrated circuit is backside processed to form a backside electrode.

32. The method of claim 25, wherein said step of thinning at least one integrated circuit is comprised of thinning at least one integrated circuit where the at least one integrated circuit is selected from the group consisting of an unbeveled integrated circuit die, a beveled integrated circuit die, an unbeveled integrated circuit wafer, a beveled integrated circuit wafer, a segment of an unbeveled integrated circuit wafer, and a segment of a beveled integrated circuit wafer.

33. The method of claim 25, further comprising the step of beveling any unbeveled at least one integrated circuit after the at least one integrated circuit is bonded to the bonding substrate and before the interconnect layer is put on the at least one integrated circuit.

34. The method of claim 25, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit of step (b) to a bonding substrate wherein said bonding substrate is selected from the group consisting of polyimide, mylar, ceramic, and semiconductor.

35. The method of claim 25, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate selected from the group consisting of a bonding substrate coated with a conducting material to provide electrical contact to a backside electrode of the tested at least one thinned integrated circuit and a bonding substrate coated with a dielectric material.

36. The method of claim 25, wherein said step of putting a layer of interconnect material over the at least one integrated circuit and dielectric material at the edge of the at least one integrated circuit is comprised of putting a layer of interconnect material over the at least one integrated circuit and dielectric material at the edge of the at least one integrated circuit using a technique selected from the group consisting of depositing an interconnect layer, laser forming an interconnect layer, and laminating a pre-formed interconnect layer.

37. The method of claim 25, wherein said step of putting a layer of dielectric material over the interconnect layer is comprised of putting a layer of dielectric material over the interconnect layer using a technique selected from the group consisting of depositing dielectric material, laser forming dielectric material, and laminating pre-formed dielectric material.

38. The method of claim 25, wherein said step of bonding the tested at least one integrated circuit to a bonding substrate comprises bonding at least two tested integrated circuits to a bonding substrate.

39. The method of claim 38, wherein said step of bonding at least two tested integrated circuits to a bonding substrate comprises bonding the at least two tested integrated circuits to a bonding substrate using a technique selected from the group consisting of butting the at least two tested integrated circuits together and overlapping the at least two tested integrated circuits.

40. The method of claim 25, wherein said step of removing the bonding substrate to form a multi-chip module is comprised of removing the bonding substrate using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.

41. The method of claim 31, wherein said step of removing the thinned at least one integrated circuit from the handle-wafer is comprised of removing the thinned at least one integrated circuit using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.

42. The method of claim 41, wherein said step of thinning at least one integrated circuit is comprised of thinning at least one integrated circuit where the at least one integrated circuit is selected from the group consisting of an unbeveled integrated circuit die, a beveled integrated circuit die, an unbeveled integrated circuit wafer, a beveled integrated circuit wafer, a segment of an unbeveled integrated circuit wafer, and a segment of a beveled integrated circuit wafer.

43. The method of claim 42, further comprising the step of beveling any unbeveled at least one integrated circuit after the at least one integrated circuit is bonded to the bonding substrate and before the interconnect layer is put on the at least one integrated circuit.

44. The method of claim 42, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit of step (b) to a bonding substrate wherein said bonding substrate is selected from the group consisting of polyimide, mylar, ceramic, and semiconductor.

45. The method of claim 44, wherein said step of bonding the tested at least one thinned integrated circuit to a bonding substrate is comprised of bonding the tested at least one thinned integrated circuit to a bonding substrate selected from the group consisting of a bonding substrate coated with a conducting material to provide electrical contact to a backside electrode of the tested at least one thinned integrated circuit and a bonding substrate coated with a dielectric material.

46. The method of claim 45, wherein said step of putting a layer of interconnect material over the at least one integrated circuit and dielectric material at the edge of the at least one integrated circuit is comprised of putting a layer of interconnect material over the at least one integrated circuit and dielectric material at the edge of the at least one integrated circuit using a technique selected from the group consisting of depositing an interconnect layer, laser forming an interconnect layer, and laminating a pre-formed interconnect layer.

47. The method of claim 46, wherein said step of putting a layer of dielectric material over the interconnect layer is comprised of putting a layer of dielectric material over the interconnect layer using a technique selected from the group consisting of depositing dielectric material, laser forming dielectric material, and laminating pre-formed dielectric material.

48. The method of claim 46, wherein said step of removing the bonding substrate to form a multi-chip module is comprised of removing the bonding substrate using a removal technique selected from the group consisting of reactive ion etching, dry chemical etching, wet chemical etching, mechanical grinding, using a release layer, and any combination thereof.