Method for forming a monolithic electronic module by dicing wafer stacks

• US 5,656,553 A
• Filed: 05/30/1996
• Issued: 08/12/1997
• Est. Priority Date: 08/22/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven Howard, Leas, James Marc
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ACOSTA GARCIA, VANESSA
• Application Number:
  US08/655,529
• Time in Patent Office: 439 Days
• Field of Search: 437/226, 437/208, 437/915, 437/227
• US Class Current: 438/15
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Claims

1. A method for forming an electronic module comprising the steps of:

(a) providing a plurality of wafers, each wafer having at least one planar array of multiple chips which has a peripheral shape;

(b) forming a wafer stack by stacking the plurality of wafers so that the at least one planar array of multiple chips of each wafer having the predefined peripheral shape align within the wafer stack; and

(c) dicing the wafer stack along the predefined peripheral shape.

2. The method of claim 1, wherein each planar array of multiple chips having the peripheral shape has an edge along said predefined peripheral shape, and wherein said method further comprises prior to said step (b) forming for each chip transfer metal connections to the edge defined along the predefined peripheral shape, and wherein said step (b) includes stacking the plurality of wafers so that the edges of the planar arrays of multiple chips containing transfer metal thereto within said wafer stack are aligned.

3. The method of claim 2, wherein after said dicing step (c), the edges of the planar arrays of multiple chips are aligned and form a common face of the electronic module, and wherein said method further comprises providing metallization on said common face to facilitate electrical connection to the chips in the electronic module.

4. The method of claim 3, wherein said providing of metallization includes providing contact pads electrically connected to transfer metals at said common face.

5. The method of claim 4, wherein said providing of metallization further comprises providing interconnect wiring on said common face to electrically interconnect chips of different planar arrays of chips disposed within the electronic module.

6. The method of claim 5, further comprising dicing the electronic module into multiple sub-modules, each sub-module comprising a plurality of chip layers, each chip layer containing at least one chip therein.

7. The method of claim 1, wherein the planar arrays of multiple chips define a common face of the electronic module subsequent to said dicing step (c), and wherein said method further comprises providing interconnect metallization on said common face subsequent to said dicing step (c).

8. The method of claim 7, further comprising dicing the electronic module into electronic sub-modules, each electronic sub-module comprising a plurality of chip layers which are at least partially interconnected by said interconnect metallization applied to the common face of the electronic module prior to said dicing thereof into said electronic sub-modules.

9. The method of claim 1, wherein each planar array of multiple chips comprises a plurality of integrated circuit (IC) chips, said IC chips having transfer wiring to a common edge disposed along said peripheral shape, and wherein said forming step (b) includes stacking the plurality of wafers such that the common edges of the planar arrays of multiple chips in different wafers align within the wafer stack.

10. The method of claim 1, wherein the predefined peripheral shape of each planar array of multiple chips comprises a non-square rectangular shape such that each planar array of chips comprises a bar-shaped planar array, and wherein said forming step (b) comprises stacking the plurality of wafers so that the bar-shaped planar arrays of different chips align within the wafer stack, and said dicing step (c) comprises dicing the wafer stack along the predefined peripheral shape such that the electronic module has two parallel edges.

11. The method of claim 1, wherein said providing step (a) includes providing the plurality of wafers such that each wafer has a plurality of bar-shaped planar arrays defined therein, said plurality of bar-shaped planar arrays being disposed identically in each wafer of the plurality of wafers, and wherein said dicing step (c) comprises dicing the wafer stack along the bar-shaped planar arrays in the wafer stack such that multiple electronic modules are formed.

12. The method of claim 11, wherein said dicing of said electronic module comprises dicing said electronic module such that each electronic sub-module formed has a plurality of chip layers with each chip layer having only one chip therein.

13. The method of claim 1, wherein said forming step (b) includes bonding the plurality of wafers together to form said wafer stack.

14. The method of claim 1, further comprising prior to said forming step (b), thinning each wafer of said plurality of wafers.

15. The method of claim 1, wherein said providing step (a) comprises testing each wafer for functionality and selecting only wafers for said forming step (b) having functional chips within said at least one planar array of multiple chips.

16. The method of claim 1, wherein each planar array of multiple chips having the peripheral shape has two opposing edges along said predefined peripheral shape, and wherein said step (c) includes dicing the wafer stack along the two opposing edges of the predefined peripheral shape.